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[74.96.87.9]) by smtp.googlemail.com with ESMTPSA id r14sm7730642qtp.56.2021.08.09.21.47.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Aug 2021 21:47:28 -0700 (PDT) From: Sean Anderson Subject: Re: [PATCH v2 3/6] riscv: lib: introduce cache_init interface To: Zong Li , rick@andestech.com, ycliang@andestech.com, bmeng.cn@gmail.com, green.wan@sifive.com, paul.walmsley@sifive.com, sjg@chromium.org, u-boot@lists.denx.de References: <20210803044444.14032-1-zong.li@sifive.com> <20210803044444.14032-4-zong.li@sifive.com> Message-ID: Date: Tue, 10 Aug 2021 00:47:28 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20210803044444.14032-4-zong.li@sifive.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 8/3/21 12:44 AM, Zong Li wrote: > Add an interface for cache initialization. Each platform can overwrite > this weak function by their own implementation, such as sifive_cache in > this patch. Can we call this enable_caches instead of cache_init? This function is called by initr_caches in board_r.c for ARM. There's even an eight-year-old TODO on the subject. > > Signed-off-by: Zong Li > --- > arch/riscv/Kconfig | 5 +++++ > arch/riscv/include/asm/cache.h | 1 + > arch/riscv/lib/Makefile | 1 + > arch/riscv/lib/cache.c | 5 +++++ > arch/riscv/lib/sifive_cache.c | 27 +++++++++++++++++++++++++++ > 5 files changed, 39 insertions(+) > create mode 100644 arch/riscv/lib/sifive_cache.c > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 4b0c3dffa6..ec651fe0a4 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT > The SiFive CLINT block holds memory-mapped control and status registers > associated with software and timer interrupts. > > +config SIFIVE_CACHE > + bool > + help > + This enables the operations to configure SiFive cache > + > config ANDES_PLIC > bool > depends on RISCV_MMODE || SPL_RISCV_MMODE > diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h > index ec8fe201d3..6ebb2b4329 100644 > --- a/arch/riscv/include/asm/cache.h > +++ b/arch/riscv/include/asm/cache.h > @@ -9,6 +9,7 @@ > > /* cache */ > void cache_flush(void); > +int cache_init(void); > > /* > * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile > index c4cc41434b..06020fcc2a 100644 > --- a/arch/riscv/lib/Makefile > +++ b/arch/riscv/lib/Makefile > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o > obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o > obj-$(CONFIG_CMD_GO) += boot.o > obj-y += cache.o > +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o > ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) > obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o > obj-$(CONFIG_ANDES_PLIC) += andes_plic.o > diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c > index b1d42bcc2b..2cd66504c6 100644 > --- a/arch/riscv/lib/cache.c > +++ b/arch/riscv/lib/cache.c > @@ -70,3 +70,8 @@ __weak int dcache_status(void) > { > return 0; > } > + > +__weak int cache_init(void) > +{ > + return 0; > +} > diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c > new file mode 100644 > index 0000000000..94e84e024e > --- /dev/null > +++ b/arch/riscv/lib/sifive_cache.c > @@ -0,0 +1,27 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2021 SiFive, Inc > + */ > + > +#include > +#include > +#include > + > +int cache_init(void) > +{ > + struct udevice *dev; > + int ret; > + > + /* Enable ways of ccache */ > + ret = uclass_get_device_by_driver(UCLASS_CACHE, > + DM_DRIVER_GET(sifive_ccache), > + &dev); > + if (ret) > + return log_msg_ret("Cannot enable cache ways", ret); > + > + ret = cache_enable(dev); > + if (ret) > + return log_msg_ret("ccache enable failed", ret); > + > + return 0; > +} > Otherwise LGTM