From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62CE3C4338F for ; Mon, 16 Aug 2021 10:05:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 474AF61AA3 for ; Mon, 16 Aug 2021 10:05:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229609AbhHPKFj (ORCPT ); Mon, 16 Aug 2021 06:05:39 -0400 Received: from ZXSHCAS2.zhaoxin.com ([203.148.12.82]:7372 "EHLO ZXSHCAS2.zhaoxin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229556AbhHPKEu (ORCPT ); Mon, 16 Aug 2021 06:04:50 -0400 Received: from zxbjmbx1.zhaoxin.com (10.29.252.163) by ZXSHCAS2.zhaoxin.com (10.28.252.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Mon, 16 Aug 2021 18:04:16 +0800 Received: from [10.32.56.37] (10.32.56.37) by zxbjmbx1.zhaoxin.com (10.29.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Mon, 16 Aug 2021 18:04:15 +0800 From: Tony W Wang-oc Subject: Re: [PATCH] rtc: Fix set RTC time delay 500ms on some Zhaoxin SOCs To: Alexandre Belloni CC: , , , , , , , , References: <1629121638-3246-1-git-send-email-TonyWWang-oc@zhaoxin.com> Message-ID: Date: Mon, 16 Aug 2021 18:03:13 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.32.56.37] X-ClientProxiedBy: ZXSHCAS2.zhaoxin.com (10.28.252.162) To zxbjmbx1.zhaoxin.com (10.29.252.163) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/08/2021 16:24, Alexandre Belloni wrote: > Hello, > > On 16/08/2021 21:47:18+0800, Tony W Wang-oc wrote: >> When the RTC divider is changed from reset to an operating time base, >> the first update cycle should be 500ms later. But on some Zhaoxin SOCs, >> this first update cycle is one second later. >> >> So set RTC time on these Zhaoxin SOCs will causing 500ms delay. >> > > Can you explain what is the relationship between writing the divider and > the 500ms delay? >> Isn't the issue that you are using systohc and set_offset_nsec is set to > NSEC_PER_SEC / 2 ? > No. When using #hwclock -s to set RTC time and set_offset_nsec is NSEC_PER_SEC / 2, the function mc146818_set_time() requires the first update cycle after RTC divider be changed from reset to an operating mode is 500ms as the MC146818A spec specified. But on some Zhaoxin SOCs, the first update cycle of RTC is one second later after RTC divider be changed from reset to an operating mode. So the first update cycle after RTC divider be changed from reset to an operation mode on These SOCs will causing 500ms delay with current mc146818_set_time() implementation. Sincerely TonyWWang-oc >> Skip setup RTC divider on these SOCs in mc146818_set_time to fix it. >> >> Signed-off-by: Tony W Wang-oc >> --- >> drivers/rtc/rtc-mc146818-lib.c | 18 ++++++++++++++++++ >> 1 file changed, 18 insertions(+) >> >> diff --git a/drivers/rtc/rtc-mc146818-lib.c b/drivers/rtc/rtc-mc146818-lib.c >> index dcfaf09..322f94b 100644 >> --- a/drivers/rtc/rtc-mc146818-lib.c >> +++ b/drivers/rtc/rtc-mc146818-lib.c >> @@ -190,8 +190,18 @@ int mc146818_set_time(struct rtc_time *time) >> spin_lock_irqsave(&rtc_lock, flags); >> save_control = CMOS_READ(RTC_CONTROL); >> CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); >> + >> +#ifdef CONFIG_X86 >> + if (!((boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR || >> + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) && >> + (boot_cpu_data.x86 <= 7 && boot_cpu_data.x86_model <= 59))) { >> + save_freq_select = CMOS_READ(RTC_FREQ_SELECT); >> + CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); >> + } >> +#else >> save_freq_select = CMOS_READ(RTC_FREQ_SELECT); >> CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); >> +#endif >> >> #ifdef CONFIG_MACH_DECSTATION >> CMOS_WRITE(real_yrs, RTC_DEC_YEAR); >> @@ -209,7 +219,15 @@ int mc146818_set_time(struct rtc_time *time) >> #endif >> >> CMOS_WRITE(save_control, RTC_CONTROL); >> + >> +#ifdef CONFIG_X86 >> + if (!((boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR || >> + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) && >> + (boot_cpu_data.x86 <= 7 && boot_cpu_data.x86_model <= 59))) >> + CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); >> +#else >> CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); >> +#endif >> >> spin_unlock_irqrestore(&rtc_lock, flags); >> >> -- >> 2.7.4 >> >