From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2AC5CA9EC3 for ; Thu, 31 Oct 2019 08:46:06 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7EC9920873 for ; Thu, 31 Oct 2019 08:46:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="C2vY/q0D" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7EC9920873 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description :Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=h2J9K8Zk9tcG1E55FzNGza4toF/w+y6OUwNWIk7sCQU=; b=C2vY/q0DUzIPeE 98gDq8+voyTa63hfDNkDJ1uUu75ItWyvhtEy3UpgsnVZ5yvCzZ/CIlrKHzxzCAUaTzXOH9HfCHj4+ x8iek/6yhs4KbQOWtNTK8X6zaHvAPCv5qlUTWCLp4TJcc+H5a7YF18UqnjSnDjGADjaMqk8IAJk9N T7nyn5Pk9SyzDSGAFr98Fd1WczwaircvfE2b+RKg+xBkfKWcycOzotV+oUlv3NKqDo2QPJ2pHB6CH AZhv54b9EWTmN3Wj410IZU+AVsQhuHZB2TYlneRkexN5Qi52hHYRX/aDV1O/PTcopTfLwnWvz/Emz SQAr+HBzjAjfdYbuQq3A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iQ65m-0002Tv-0l; Thu, 31 Oct 2019 08:46:06 +0000 Received: from szxga05-in.huawei.com ([45.249.212.191] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iQ65i-0002TN-Sf for linux-arm-kernel@lists.infradead.org; Thu, 31 Oct 2019 08:46:04 +0000 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 7E79336CC2BF1554C2DA; Thu, 31 Oct 2019 16:45:58 +0800 (CST) Received: from [127.0.0.1] (10.74.221.148) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Thu, 31 Oct 2019 16:45:52 +0800 Subject: Re: [PATCH] arm64: perf: Simplify the ARMv8 PMUv3 event attributes To: Richard Henderson , References: <1572407177-48229-1-git-send-email-zhangshaokun@hisilicon.com> From: Shaokun Zhang Message-ID: Date: Thu, 31 Oct 2019 16:45:52 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.74.221.148] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191031_014603_103250_BF294233 X-CRM114-Status: GOOD ( 12.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Will Deacon Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Richard, Thanks your comments and Mark has helped to reply some. On 2019/10/30 21:34, Richard Henderson wrote: > On 10/30/19 4:46 AM, Shaokun Zhang wrote: >> For each PMU event, there is a ARMV8_EVENT_ATTR(xx, XX) and >> &armv8_event_attr_xx.attr.attr. Let's redefine the ARMV8_EVENT_ATTR >> to simplify the armv8_pmuv3_event_attrs. > ... >> #define ARMV8_EVENT_ATTR(name, config) \ >> + (&((struct perf_pmu_events_attr[]) { \ >> + { .attr = __ATTR(name, 0444, armv8pmu_events_sysfs_show, NULL), \ >> + .id = config, } \ >> + })[0].attr.attr) >> >> static struct attribute *armv8_pmuv3_event_attrs[] = { >> + ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR), > > You do realize this creates complete perf_pmu_events_attr structures, most of > which is unused and unreachable, right? > > Also, why not take the opportunity to assert that the armv8_pmuv3_event_attrs > array cannot get out of sync with the ARMV8_PMUV3_* defines? > For my initial purpose: remove the &armv8_event_attr_xx.attr.attr and only maintain the armv8_pmuv3_event_attrs array directly when we want to add one new PMU event. For example: #define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A ..... static struct attribute *armv8_pmuv3_event_attrs[] = { ...... ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED), NULL, }; Thanks, Shaokun > Slightly better would seem to be > > #define ARMV8_EVENT_ATTR(name, config) \ > [config] = &((struct device_attribute) \ > __ATTR(name, 0444, armv8pmu_events_sysfs_show, NULL)).attr > > though I'm not sure why __ATTR is particularly desired above > > #define ARMV8_EVENT_ATTR(name, config) \ > [config] = &(struct attribute){ \ > .name = __stringify(name), \ > .mode = 0444, \ > } > > > r~ > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel