* [PATCH 0/4] mailbox: imx: add i.MX8ULP MU support
@ 2021-05-07 10:19 ` Peng Fan (OSS)
0 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-07 10:19 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kernel, festevam, aisheng.dong, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
i.MX8ULP generic MU is a different IP compared with previous i.MX chips.
It has different register layout and bit position, but the register name
and bit definitions are almost same with previous i.MX MU.
So we extend the current imx-mailbox driver to support i.MX8ULP.
Peng Fan (4):
dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
mailbox: imx: replace the xTR/xRR array with single register
mailbox: imx: add xSR/xCR register array
mailbox: imx-mailbox: support i.MX8ULP MU
.../devicetree/bindings/mailbox/fsl,mu.yaml | 1 +
drivers/mailbox/imx-mailbox.c | 196 +++++++++++-------
2 files changed, 123 insertions(+), 74 deletions(-)
--
2.30.0
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 0/4] mailbox: imx: add i.MX8ULP MU support
@ 2021-05-07 10:19 ` Peng Fan (OSS)
0 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-07 10:19 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kernel, festevam, aisheng.dong, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
i.MX8ULP generic MU is a different IP compared with previous i.MX chips.
It has different register layout and bit position, but the register name
and bit definitions are almost same with previous i.MX MU.
So we extend the current imx-mailbox driver to support i.MX8ULP.
Peng Fan (4):
dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
mailbox: imx: replace the xTR/xRR array with single register
mailbox: imx: add xSR/xCR register array
mailbox: imx-mailbox: support i.MX8ULP MU
.../devicetree/bindings/mailbox/fsl,mu.yaml | 1 +
drivers/mailbox/imx-mailbox.c | 196 +++++++++++-------
2 files changed, 123 insertions(+), 74 deletions(-)
--
2.30.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/4] dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
2021-05-07 10:19 ` Peng Fan (OSS)
@ 2021-05-07 10:19 ` Peng Fan (OSS)
-1 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-07 10:19 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kernel, festevam, aisheng.dong, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
The register layout and bits definition of i.MX8ULP MU is different
compared with others, let's add the compatible for the new MU.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
index 1a3dff277e2b..675ad9de15bb 100644
--- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
+++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
@@ -26,6 +26,7 @@ properties:
oneOf:
- const: fsl,imx6sx-mu
- const: fsl,imx7ulp-mu
+ - const: fsl,imx8ulp-mu
- const: fsl,imx8-mu-scu
- items:
- enum:
--
2.30.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 1/4] dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
@ 2021-05-07 10:19 ` Peng Fan (OSS)
0 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-07 10:19 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kernel, festevam, aisheng.dong, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
The register layout and bits definition of i.MX8ULP MU is different
compared with others, let's add the compatible for the new MU.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
index 1a3dff277e2b..675ad9de15bb 100644
--- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
+++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
@@ -26,6 +26,7 @@ properties:
oneOf:
- const: fsl,imx6sx-mu
- const: fsl,imx7ulp-mu
+ - const: fsl,imx8ulp-mu
- const: fsl,imx8-mu-scu
- items:
- enum:
--
2.30.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/4] mailbox: imx: replace the xTR/xRR array with single register
2021-05-07 10:19 ` Peng Fan (OSS)
@ 2021-05-07 10:19 ` Peng Fan (OSS)
-1 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-07 10:19 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kernel, festevam, aisheng.dong, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
The xTR/xRR registers are using 4 bytes stride and continuous.
Considering we will support more TR and RR registers, use base + idx * 4
method to calculate register address, not hardcoding in driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/mailbox/imx-mailbox.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index 2543c7b6948b..bd7758c32a80 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -76,8 +76,8 @@ struct imx_mu_dcfg {
int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
void (*init)(struct imx_mu_priv *priv);
- u32 xTR[4]; /* Transmit Registers */
- u32 xRR[4]; /* Receive Registers */
+ u32 xTR; /* Transmit Register0 */
+ u32 xRR; /* Receive Register0 */
u32 xSR; /* Status Register */
u32 xCR; /* Control Register */
};
@@ -120,7 +120,7 @@ static int imx_mu_generic_tx(struct imx_mu_priv *priv,
switch (cp->type) {
case IMX_MU_TYPE_TX:
- imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
+ imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
break;
case IMX_MU_TYPE_TXDB:
@@ -140,7 +140,7 @@ static int imx_mu_generic_rx(struct imx_mu_priv *priv,
{
u32 dat;
- dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
+ dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
mbox_chan_received_data(cp->chan, (void *)&dat);
return 0;
@@ -172,7 +172,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
}
for (i = 0; i < 4 && i < msg->hdr.size; i++)
- imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
+ imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
for (; i < msg->hdr.size; i++) {
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
xsr,
@@ -182,7 +182,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
dev_err(priv->dev, "Send data index: %d timeout\n", i);
return ret;
}
- imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
+ imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
}
imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
@@ -204,7 +204,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
u32 xsr;
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
- *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
+ *data++ = imx_mu_read(priv, priv->dcfg->xRR);
if (msg.hdr.size > sizeof(msg) / 4) {
dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
@@ -218,7 +218,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
dev_err(priv->dev, "timeout read idx %d\n", i);
return ret;
}
- *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
+ *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
}
imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
@@ -564,8 +564,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
.tx = imx_mu_generic_tx,
.rx = imx_mu_generic_rx,
.init = imx_mu_init_generic,
- .xTR = {0x0, 0x4, 0x8, 0xc},
- .xRR = {0x10, 0x14, 0x18, 0x1c},
+ .xTR = 0x0,
+ .xRR = 0x10,
.xSR = 0x20,
.xCR = 0x24,
};
@@ -574,8 +574,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
.tx = imx_mu_generic_tx,
.rx = imx_mu_generic_rx,
.init = imx_mu_init_generic,
- .xTR = {0x20, 0x24, 0x28, 0x2c},
- .xRR = {0x40, 0x44, 0x48, 0x4c},
+ .xTR = 0x20,
+ .xRR = 0x40,
.xSR = 0x60,
.xCR = 0x64,
};
@@ -584,8 +584,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
.tx = imx_mu_scu_tx,
.rx = imx_mu_scu_rx,
.init = imx_mu_init_scu,
- .xTR = {0x0, 0x4, 0x8, 0xc},
- .xRR = {0x10, 0x14, 0x18, 0x1c},
+ .xTR = 0x0
+ .xRR = 0x10
.xSR = 0x20,
.xCR = 0x24,
};
--
2.30.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/4] mailbox: imx: replace the xTR/xRR array with single register
@ 2021-05-07 10:19 ` Peng Fan (OSS)
0 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-07 10:19 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kernel, festevam, aisheng.dong, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
The xTR/xRR registers are using 4 bytes stride and continuous.
Considering we will support more TR and RR registers, use base + idx * 4
method to calculate register address, not hardcoding in driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/mailbox/imx-mailbox.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index 2543c7b6948b..bd7758c32a80 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -76,8 +76,8 @@ struct imx_mu_dcfg {
int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
void (*init)(struct imx_mu_priv *priv);
- u32 xTR[4]; /* Transmit Registers */
- u32 xRR[4]; /* Receive Registers */
+ u32 xTR; /* Transmit Register0 */
+ u32 xRR; /* Receive Register0 */
u32 xSR; /* Status Register */
u32 xCR; /* Control Register */
};
@@ -120,7 +120,7 @@ static int imx_mu_generic_tx(struct imx_mu_priv *priv,
switch (cp->type) {
case IMX_MU_TYPE_TX:
- imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
+ imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
break;
case IMX_MU_TYPE_TXDB:
@@ -140,7 +140,7 @@ static int imx_mu_generic_rx(struct imx_mu_priv *priv,
{
u32 dat;
- dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
+ dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
mbox_chan_received_data(cp->chan, (void *)&dat);
return 0;
@@ -172,7 +172,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
}
for (i = 0; i < 4 && i < msg->hdr.size; i++)
- imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
+ imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
for (; i < msg->hdr.size; i++) {
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
xsr,
@@ -182,7 +182,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
dev_err(priv->dev, "Send data index: %d timeout\n", i);
return ret;
}
- imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
+ imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
}
imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
@@ -204,7 +204,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
u32 xsr;
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
- *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
+ *data++ = imx_mu_read(priv, priv->dcfg->xRR);
if (msg.hdr.size > sizeof(msg) / 4) {
dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
@@ -218,7 +218,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
dev_err(priv->dev, "timeout read idx %d\n", i);
return ret;
}
- *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
+ *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
}
imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
@@ -564,8 +564,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
.tx = imx_mu_generic_tx,
.rx = imx_mu_generic_rx,
.init = imx_mu_init_generic,
- .xTR = {0x0, 0x4, 0x8, 0xc},
- .xRR = {0x10, 0x14, 0x18, 0x1c},
+ .xTR = 0x0,
+ .xRR = 0x10,
.xSR = 0x20,
.xCR = 0x24,
};
@@ -574,8 +574,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
.tx = imx_mu_generic_tx,
.rx = imx_mu_generic_rx,
.init = imx_mu_init_generic,
- .xTR = {0x20, 0x24, 0x28, 0x2c},
- .xRR = {0x40, 0x44, 0x48, 0x4c},
+ .xTR = 0x20,
+ .xRR = 0x40,
.xSR = 0x60,
.xCR = 0x64,
};
@@ -584,8 +584,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
.tx = imx_mu_scu_tx,
.rx = imx_mu_scu_rx,
.init = imx_mu_init_scu,
- .xTR = {0x0, 0x4, 0x8, 0xc},
- .xRR = {0x10, 0x14, 0x18, 0x1c},
+ .xTR = 0x0
+ .xRR = 0x10
.xSR = 0x20,
.xCR = 0x24,
};
--
2.30.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/4] mailbox: imx: add xSR/xCR register array
2021-05-07 10:19 ` Peng Fan (OSS)
@ 2021-05-07 10:19 ` Peng Fan (OSS)
-1 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-07 10:19 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kernel, festevam, aisheng.dong, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
We are going to add a new platform which has 4 status registers(SR, TSR,
RSR, GSR) and 4 control registers(CR, TCR, RCR, GCR), so extend xSR
and xCR to register array and adapt code to use it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/mailbox/imx-mailbox.c | 96 ++++++++++++++++++++++-------------
1 file changed, 61 insertions(+), 35 deletions(-)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index bd7758c32a80..f5dadcc827aa 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -41,6 +41,21 @@ enum imx_mu_chan_type {
IMX_MU_TYPE_RXDB, /* Rx doorbell */
};
+enum imx_mu_xcr {
+ IMX_MU_CR,
+ IMX_MU_GCR,
+ IMX_MU_TCR,
+ IMX_MU_RCR,
+ IMX_MU_xCR_MAX,
+};
+
+enum imx_mu_xsr {
+ IMX_MU_SR,
+ IMX_MU_GSR,
+ IMX_MU_TSR,
+ IMX_MU_RSR,
+};
+
struct imx_sc_rpc_msg_max {
struct imx_sc_rpc_msg hdr;
u32 data[7];
@@ -67,7 +82,7 @@ struct imx_mu_priv {
struct clk *clk;
int irq;
- u32 xcr;
+ u32 xcr[4];
bool side_b;
};
@@ -78,8 +93,8 @@ struct imx_mu_dcfg {
void (*init)(struct imx_mu_priv *priv);
u32 xTR; /* Transmit Register0 */
u32 xRR; /* Receive Register0 */
- u32 xSR; /* Status Register */
- u32 xCR; /* Control Register */
+ u32 xSR[4]; /* Status Registers */
+ u32 xCR[4]; /* Control Registers */
};
static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
@@ -97,16 +112,16 @@ static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
return ioread32(priv->base + offs);
}
-static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
+static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&priv->xcr_lock, flags);
- val = imx_mu_read(priv, priv->dcfg->xCR);
+ val = imx_mu_read(priv, priv->dcfg->xCR[type]);
val &= ~clr;
val |= set;
- imx_mu_write(priv, val, priv->dcfg->xCR);
+ imx_mu_write(priv, val, priv->dcfg->xCR[type]);
spin_unlock_irqrestore(&priv->xcr_lock, flags);
return val;
@@ -121,10 +136,10 @@ static int imx_mu_generic_tx(struct imx_mu_priv *priv,
switch (cp->type) {
case IMX_MU_TYPE_TX:
imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
- imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(cp->idx), 0);
break;
case IMX_MU_TYPE_TXDB:
- imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(cp->idx), 0);
tasklet_schedule(&cp->txdb_tasklet);
break;
default:
@@ -174,7 +189,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
for (i = 0; i < 4 && i < msg->hdr.size; i++)
imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
for (; i < msg->hdr.size; i++) {
- ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
+ ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
xsr,
xsr & IMX_MU_xSR_TEn(i % 4),
0, 100);
@@ -185,7 +200,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
}
- imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(cp->idx), 0);
break;
default:
dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
@@ -203,7 +218,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
int i, ret;
u32 xsr;
- imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(0));
*data++ = imx_mu_read(priv, priv->dcfg->xRR);
if (msg.hdr.size > sizeof(msg) / 4) {
@@ -212,7 +227,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
}
for (i = 1; i < msg.hdr.size; i++) {
- ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr,
+ ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
if (ret) {
dev_err(priv->dev, "timeout read idx %d\n", i);
@@ -221,7 +236,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
}
- imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(0), 0);
mbox_chan_received_data(cp->chan, (void *)&msg);
return 0;
@@ -241,19 +256,22 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
struct imx_mu_con_priv *cp = chan->con_priv;
u32 val, ctrl;
- ctrl = imx_mu_read(priv, priv->dcfg->xCR);
- val = imx_mu_read(priv, priv->dcfg->xSR);
-
switch (cp->type) {
case IMX_MU_TYPE_TX:
+ ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
+ val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
val &= IMX_MU_xSR_TEn(cp->idx) &
(ctrl & IMX_MU_xCR_TIEn(cp->idx));
break;
case IMX_MU_TYPE_RX:
+ ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
+ val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
val &= IMX_MU_xSR_RFn(cp->idx) &
(ctrl & IMX_MU_xCR_RIEn(cp->idx));
break;
case IMX_MU_TYPE_RXDB:
+ ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GCR]);
+ val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
val &= IMX_MU_xSR_GIPn(cp->idx) &
(ctrl & IMX_MU_xCR_GIEn(cp->idx));
break;
@@ -265,12 +283,12 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
return IRQ_NONE;
if (val == IMX_MU_xSR_TEn(cp->idx)) {
- imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
mbox_chan_txdone(chan, 0);
} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
priv->dcfg->rx(priv, cp);
} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
- imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
+ imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR[IMX_MU_GSR]);
mbox_chan_received_data(chan, NULL);
} else {
dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
@@ -317,10 +335,10 @@ static int imx_mu_startup(struct mbox_chan *chan)
switch (cp->type) {
case IMX_MU_TYPE_RX:
- imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(cp->idx), 0);
break;
case IMX_MU_TYPE_RXDB:
- imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIEn(cp->idx), 0);
break;
default:
break;
@@ -342,13 +360,13 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
switch (cp->type) {
case IMX_MU_TYPE_TX:
- imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
break;
case IMX_MU_TYPE_RX:
- imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(cp->idx));
break;
case IMX_MU_TYPE_RXDB:
- imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_GCR, 0, IMX_MU_xCR_GIEn(cp->idx));
break;
default:
break;
@@ -444,7 +462,8 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
return;
/* Set default MU configuration */
- imx_mu_write(priv, 0, priv->dcfg->xCR);
+ for (i = 0; i < IMX_MU_xCR_MAX; i++)
+ imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
}
static void imx_mu_init_scu(struct imx_mu_priv *priv)
@@ -466,7 +485,8 @@ static void imx_mu_init_scu(struct imx_mu_priv *priv)
priv->mbox.of_xlate = imx_mu_scu_xlate;
/* Set default MU configuration */
- imx_mu_write(priv, 0, priv->dcfg->xCR);
+ for (i = 0; i < IMX_MU_xCR_MAX; i++)
+ imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
}
static int imx_mu_probe(struct platform_device *pdev)
@@ -566,8 +586,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
.init = imx_mu_init_generic,
.xTR = 0x0,
.xRR = 0x10,
- .xSR = 0x20,
- .xCR = 0x24,
+ .xSR = {0x20, 0x20, 0x20, 0x20},
+ .xCR = {0x24, 0x24, 0x24, 0x24},
};
static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
@@ -576,8 +596,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
.init = imx_mu_init_generic,
.xTR = 0x20,
.xRR = 0x40,
- .xSR = 0x60,
- .xCR = 0x64,
+ .xSR = {0x60, 0x60, 0x60, 0x60},
+ .xCR = {0x64, 0x64, 0x64, 0x64},
};
static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
@@ -586,8 +606,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
.init = imx_mu_init_scu,
.xTR = 0x0
.xRR = 0x10
- .xSR = 0x20,
- .xCR = 0x24,
+ .xSR = {0x20, 0x20, 0x20, 0x20},
+ .xCR = {0x24, 0x24, 0x24, 0x24},
};
static const struct of_device_id imx_mu_dt_ids[] = {
@@ -601,9 +621,12 @@ MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
{
struct imx_mu_priv *priv = dev_get_drvdata(dev);
+ int i;
- if (!priv->clk)
- priv->xcr = imx_mu_read(priv, priv->dcfg->xCR);
+ if (!priv->clk) {
+ for (i = 0; i < IMX_MU_xCR_MAX; i++)
+ priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
+ }
return 0;
}
@@ -611,6 +634,7 @@ static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
{
struct imx_mu_priv *priv = dev_get_drvdata(dev);
+ int i;
/*
* ONLY restore MU when context lost, the TIE could
@@ -620,8 +644,10 @@ static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
* send failed, may lead to system freeze. This issue
* is observed by testing freeze mode suspend.
*/
- if (!imx_mu_read(priv, priv->dcfg->xCR) && !priv->clk)
- imx_mu_write(priv, priv->xcr, priv->dcfg->xCR);
+ if (!imx_mu_read(priv, priv->dcfg->xCR[0]) && !priv->clk) {
+ for (i = 0; i < IMX_MU_xCR_MAX; i++)
+ imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);
+ }
return 0;
}
--
2.30.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/4] mailbox: imx: add xSR/xCR register array
@ 2021-05-07 10:19 ` Peng Fan (OSS)
0 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-07 10:19 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kernel, festevam, aisheng.dong, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
We are going to add a new platform which has 4 status registers(SR, TSR,
RSR, GSR) and 4 control registers(CR, TCR, RCR, GCR), so extend xSR
and xCR to register array and adapt code to use it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/mailbox/imx-mailbox.c | 96 ++++++++++++++++++++++-------------
1 file changed, 61 insertions(+), 35 deletions(-)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index bd7758c32a80..f5dadcc827aa 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -41,6 +41,21 @@ enum imx_mu_chan_type {
IMX_MU_TYPE_RXDB, /* Rx doorbell */
};
+enum imx_mu_xcr {
+ IMX_MU_CR,
+ IMX_MU_GCR,
+ IMX_MU_TCR,
+ IMX_MU_RCR,
+ IMX_MU_xCR_MAX,
+};
+
+enum imx_mu_xsr {
+ IMX_MU_SR,
+ IMX_MU_GSR,
+ IMX_MU_TSR,
+ IMX_MU_RSR,
+};
+
struct imx_sc_rpc_msg_max {
struct imx_sc_rpc_msg hdr;
u32 data[7];
@@ -67,7 +82,7 @@ struct imx_mu_priv {
struct clk *clk;
int irq;
- u32 xcr;
+ u32 xcr[4];
bool side_b;
};
@@ -78,8 +93,8 @@ struct imx_mu_dcfg {
void (*init)(struct imx_mu_priv *priv);
u32 xTR; /* Transmit Register0 */
u32 xRR; /* Receive Register0 */
- u32 xSR; /* Status Register */
- u32 xCR; /* Control Register */
+ u32 xSR[4]; /* Status Registers */
+ u32 xCR[4]; /* Control Registers */
};
static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
@@ -97,16 +112,16 @@ static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
return ioread32(priv->base + offs);
}
-static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
+static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&priv->xcr_lock, flags);
- val = imx_mu_read(priv, priv->dcfg->xCR);
+ val = imx_mu_read(priv, priv->dcfg->xCR[type]);
val &= ~clr;
val |= set;
- imx_mu_write(priv, val, priv->dcfg->xCR);
+ imx_mu_write(priv, val, priv->dcfg->xCR[type]);
spin_unlock_irqrestore(&priv->xcr_lock, flags);
return val;
@@ -121,10 +136,10 @@ static int imx_mu_generic_tx(struct imx_mu_priv *priv,
switch (cp->type) {
case IMX_MU_TYPE_TX:
imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
- imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(cp->idx), 0);
break;
case IMX_MU_TYPE_TXDB:
- imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(cp->idx), 0);
tasklet_schedule(&cp->txdb_tasklet);
break;
default:
@@ -174,7 +189,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
for (i = 0; i < 4 && i < msg->hdr.size; i++)
imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
for (; i < msg->hdr.size; i++) {
- ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
+ ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
xsr,
xsr & IMX_MU_xSR_TEn(i % 4),
0, 100);
@@ -185,7 +200,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
}
- imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(cp->idx), 0);
break;
default:
dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
@@ -203,7 +218,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
int i, ret;
u32 xsr;
- imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(0));
*data++ = imx_mu_read(priv, priv->dcfg->xRR);
if (msg.hdr.size > sizeof(msg) / 4) {
@@ -212,7 +227,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
}
for (i = 1; i < msg.hdr.size; i++) {
- ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr,
+ ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
if (ret) {
dev_err(priv->dev, "timeout read idx %d\n", i);
@@ -221,7 +236,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
}
- imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(0), 0);
mbox_chan_received_data(cp->chan, (void *)&msg);
return 0;
@@ -241,19 +256,22 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
struct imx_mu_con_priv *cp = chan->con_priv;
u32 val, ctrl;
- ctrl = imx_mu_read(priv, priv->dcfg->xCR);
- val = imx_mu_read(priv, priv->dcfg->xSR);
-
switch (cp->type) {
case IMX_MU_TYPE_TX:
+ ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
+ val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
val &= IMX_MU_xSR_TEn(cp->idx) &
(ctrl & IMX_MU_xCR_TIEn(cp->idx));
break;
case IMX_MU_TYPE_RX:
+ ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
+ val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
val &= IMX_MU_xSR_RFn(cp->idx) &
(ctrl & IMX_MU_xCR_RIEn(cp->idx));
break;
case IMX_MU_TYPE_RXDB:
+ ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GCR]);
+ val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
val &= IMX_MU_xSR_GIPn(cp->idx) &
(ctrl & IMX_MU_xCR_GIEn(cp->idx));
break;
@@ -265,12 +283,12 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
return IRQ_NONE;
if (val == IMX_MU_xSR_TEn(cp->idx)) {
- imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
mbox_chan_txdone(chan, 0);
} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
priv->dcfg->rx(priv, cp);
} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
- imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
+ imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR[IMX_MU_GSR]);
mbox_chan_received_data(chan, NULL);
} else {
dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
@@ -317,10 +335,10 @@ static int imx_mu_startup(struct mbox_chan *chan)
switch (cp->type) {
case IMX_MU_TYPE_RX:
- imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(cp->idx), 0);
break;
case IMX_MU_TYPE_RXDB:
- imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIEn(cp->idx), 0);
break;
default:
break;
@@ -342,13 +360,13 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
switch (cp->type) {
case IMX_MU_TYPE_TX:
- imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
break;
case IMX_MU_TYPE_RX:
- imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(cp->idx));
break;
case IMX_MU_TYPE_RXDB:
- imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_GCR, 0, IMX_MU_xCR_GIEn(cp->idx));
break;
default:
break;
@@ -444,7 +462,8 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
return;
/* Set default MU configuration */
- imx_mu_write(priv, 0, priv->dcfg->xCR);
+ for (i = 0; i < IMX_MU_xCR_MAX; i++)
+ imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
}
static void imx_mu_init_scu(struct imx_mu_priv *priv)
@@ -466,7 +485,8 @@ static void imx_mu_init_scu(struct imx_mu_priv *priv)
priv->mbox.of_xlate = imx_mu_scu_xlate;
/* Set default MU configuration */
- imx_mu_write(priv, 0, priv->dcfg->xCR);
+ for (i = 0; i < IMX_MU_xCR_MAX; i++)
+ imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
}
static int imx_mu_probe(struct platform_device *pdev)
@@ -566,8 +586,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
.init = imx_mu_init_generic,
.xTR = 0x0,
.xRR = 0x10,
- .xSR = 0x20,
- .xCR = 0x24,
+ .xSR = {0x20, 0x20, 0x20, 0x20},
+ .xCR = {0x24, 0x24, 0x24, 0x24},
};
static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
@@ -576,8 +596,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
.init = imx_mu_init_generic,
.xTR = 0x20,
.xRR = 0x40,
- .xSR = 0x60,
- .xCR = 0x64,
+ .xSR = {0x60, 0x60, 0x60, 0x60},
+ .xCR = {0x64, 0x64, 0x64, 0x64},
};
static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
@@ -586,8 +606,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
.init = imx_mu_init_scu,
.xTR = 0x0
.xRR = 0x10
- .xSR = 0x20,
- .xCR = 0x24,
+ .xSR = {0x20, 0x20, 0x20, 0x20},
+ .xCR = {0x24, 0x24, 0x24, 0x24},
};
static const struct of_device_id imx_mu_dt_ids[] = {
@@ -601,9 +621,12 @@ MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
{
struct imx_mu_priv *priv = dev_get_drvdata(dev);
+ int i;
- if (!priv->clk)
- priv->xcr = imx_mu_read(priv, priv->dcfg->xCR);
+ if (!priv->clk) {
+ for (i = 0; i < IMX_MU_xCR_MAX; i++)
+ priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
+ }
return 0;
}
@@ -611,6 +634,7 @@ static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
{
struct imx_mu_priv *priv = dev_get_drvdata(dev);
+ int i;
/*
* ONLY restore MU when context lost, the TIE could
@@ -620,8 +644,10 @@ static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
* send failed, may lead to system freeze. This issue
* is observed by testing freeze mode suspend.
*/
- if (!imx_mu_read(priv, priv->dcfg->xCR) && !priv->clk)
- imx_mu_write(priv, priv->xcr, priv->dcfg->xCR);
+ if (!imx_mu_read(priv, priv->dcfg->xCR[0]) && !priv->clk) {
+ for (i = 0; i < IMX_MU_xCR_MAX; i++)
+ imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);
+ }
return 0;
}
--
2.30.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/4] mailbox: imx-mailbox: support i.MX8ULP MU
2021-05-07 10:19 ` Peng Fan (OSS)
@ 2021-05-07 10:19 ` Peng Fan (OSS)
-1 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-07 10:19 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kernel, festevam, aisheng.dong, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
i.MX8ULP MU has different register layout and bit layout compared
with i.MX6SX/7ULP/8.
So add enum imx_mu_type to show it is IMX_MU_V2 or IMX_MU_V1.
For IMX_MU_V2 mu hardware, check it when calculating bit offset to get
the correct offset.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/mailbox/imx-mailbox.c | 100 +++++++++++++++++++++-------------
1 file changed, 61 insertions(+), 39 deletions(-)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index f5dadcc827aa..7fc5b4c2d3af 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -15,20 +15,6 @@
#include <linux/pm_runtime.h>
#include <linux/slab.h>
-#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
-#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
-#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
-#define IMX_MU_xSR_BRDIP BIT(9)
-
-/* General Purpose Interrupt Enable */
-#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
-/* Receive Interrupt Enable */
-#define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
-/* Transmit Interrupt Enable */
-#define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
-/* General Purpose Interrupt Request */
-#define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
-
#define IMX_MU_CHANS 16
/* TX0/RX0/RXDB[0-3] */
#define IMX_MU_SCU_CHANS 6
@@ -87,16 +73,36 @@ struct imx_mu_priv {
bool side_b;
};
+enum imx_mu_type {
+ IMX_MU_V1,
+ IMX_MU_V2,
+};
+
struct imx_mu_dcfg {
int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
void (*init)(struct imx_mu_priv *priv);
+ enum imx_mu_type type;
u32 xTR; /* Transmit Register0 */
u32 xRR; /* Receive Register0 */
u32 xSR[4]; /* Status Registers */
u32 xCR[4]; /* Control Registers */
};
+#define IMX_MU_xSR_GIPn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
+#define IMX_MU_xSR_RFn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
+#define IMX_MU_xSR_TEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
+
+/* General Purpose Interrupt Enable */
+#define IMX_MU_xCR_GIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
+/* Receive Interrupt Enable */
+#define IMX_MU_xCR_RIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
+/* Transmit Interrupt Enable */
+#define IMX_MU_xCR_TIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
+/* General Purpose Interrupt Request */
+#define IMX_MU_xCR_GIRn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
+
+
static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
{
return container_of(mbox, struct imx_mu_priv, mbox);
@@ -136,10 +142,10 @@ static int imx_mu_generic_tx(struct imx_mu_priv *priv,
switch (cp->type) {
case IMX_MU_TYPE_TX:
imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
- imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
break;
case IMX_MU_TYPE_TXDB:
- imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
tasklet_schedule(&cp->txdb_tasklet);
break;
default:
@@ -191,7 +197,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
for (; i < msg->hdr.size; i++) {
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
xsr,
- xsr & IMX_MU_xSR_TEn(i % 4),
+ xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % 4),
0, 100);
if (ret) {
dev_err(priv->dev, "Send data index: %d timeout\n", i);
@@ -200,7 +206,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
}
- imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
break;
default:
dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
@@ -218,7 +224,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
int i, ret;
u32 xsr;
- imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(0));
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
*data++ = imx_mu_read(priv, priv->dcfg->xRR);
if (msg.hdr.size > sizeof(msg) / 4) {
@@ -228,7 +234,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
for (i = 1; i < msg.hdr.size; i++) {
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
- xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
+ xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, 100);
if (ret) {
dev_err(priv->dev, "timeout read idx %d\n", i);
return ret;
@@ -236,7 +242,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
}
- imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(0), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
mbox_chan_received_data(cp->chan, (void *)&msg);
return 0;
@@ -260,20 +266,20 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
case IMX_MU_TYPE_TX:
ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
- val &= IMX_MU_xSR_TEn(cp->idx) &
- (ctrl & IMX_MU_xCR_TIEn(cp->idx));
+ val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
+ (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
break;
case IMX_MU_TYPE_RX:
ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
- val &= IMX_MU_xSR_RFn(cp->idx) &
- (ctrl & IMX_MU_xCR_RIEn(cp->idx));
+ val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
+ (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
break;
case IMX_MU_TYPE_RXDB:
ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GCR]);
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
- val &= IMX_MU_xSR_GIPn(cp->idx) &
- (ctrl & IMX_MU_xCR_GIEn(cp->idx));
+ val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
+ (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
break;
default:
break;
@@ -282,13 +288,17 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
if (!val)
return IRQ_NONE;
- if (val == IMX_MU_xSR_TEn(cp->idx)) {
- imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
+ if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
+ (cp->type == IMX_MU_TYPE_TX)) {
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
mbox_chan_txdone(chan, 0);
- } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
+ } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
+ (cp->type == IMX_MU_TYPE_RX)) {
priv->dcfg->rx(priv, cp);
- } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
- imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR[IMX_MU_GSR]);
+ } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
+ (cp->type == IMX_MU_TYPE_RXDB)) {
+ imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
+ priv->dcfg->xSR[IMX_MU_GSR]);
mbox_chan_received_data(chan, NULL);
} else {
dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
@@ -335,10 +345,10 @@ static int imx_mu_startup(struct mbox_chan *chan)
switch (cp->type) {
case IMX_MU_TYPE_RX:
- imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
break;
case IMX_MU_TYPE_RXDB:
- imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
break;
default:
break;
@@ -360,13 +370,13 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
switch (cp->type) {
case IMX_MU_TYPE_TX:
- imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
break;
case IMX_MU_TYPE_RX:
- imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
break;
case IMX_MU_TYPE_RXDB:
- imx_mu_xcr_rmw(priv, IMX_MU_GCR, 0, IMX_MU_xCR_GIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_GCR, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
break;
default:
break;
@@ -600,12 +610,23 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
.xCR = {0x64, 0x64, 0x64, 0x64},
};
+static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
+ .tx = imx_mu_generic_tx,
+ .rx = imx_mu_generic_rx,
+ .init = imx_mu_init_generic,
+ .type = IMX_MU_V2,
+ .xTR = 0x200,
+ .xRR = 0x280,
+ .xSR = {0xC, 0x118, 0x124, 0x12C},
+ .xCR = {0x8, 0x114, 0x120, 0x128},
+};
+
static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
.tx = imx_mu_scu_tx,
.rx = imx_mu_scu_rx,
.init = imx_mu_init_scu,
- .xTR = 0x0
- .xRR = 0x10
+ .xTR = 0x0,
+ .xRR = 0x10,
.xSR = {0x20, 0x20, 0x20, 0x20},
.xCR = {0x24, 0x24, 0x24, 0x24},
};
@@ -613,6 +634,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
static const struct of_device_id imx_mu_dt_ids[] = {
{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
+ { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
{ },
};
--
2.30.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/4] mailbox: imx-mailbox: support i.MX8ULP MU
@ 2021-05-07 10:19 ` Peng Fan (OSS)
0 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-07 10:19 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kernel, festevam, aisheng.dong, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
i.MX8ULP MU has different register layout and bit layout compared
with i.MX6SX/7ULP/8.
So add enum imx_mu_type to show it is IMX_MU_V2 or IMX_MU_V1.
For IMX_MU_V2 mu hardware, check it when calculating bit offset to get
the correct offset.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/mailbox/imx-mailbox.c | 100 +++++++++++++++++++++-------------
1 file changed, 61 insertions(+), 39 deletions(-)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index f5dadcc827aa..7fc5b4c2d3af 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -15,20 +15,6 @@
#include <linux/pm_runtime.h>
#include <linux/slab.h>
-#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
-#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
-#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
-#define IMX_MU_xSR_BRDIP BIT(9)
-
-/* General Purpose Interrupt Enable */
-#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
-/* Receive Interrupt Enable */
-#define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
-/* Transmit Interrupt Enable */
-#define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
-/* General Purpose Interrupt Request */
-#define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
-
#define IMX_MU_CHANS 16
/* TX0/RX0/RXDB[0-3] */
#define IMX_MU_SCU_CHANS 6
@@ -87,16 +73,36 @@ struct imx_mu_priv {
bool side_b;
};
+enum imx_mu_type {
+ IMX_MU_V1,
+ IMX_MU_V2,
+};
+
struct imx_mu_dcfg {
int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
void (*init)(struct imx_mu_priv *priv);
+ enum imx_mu_type type;
u32 xTR; /* Transmit Register0 */
u32 xRR; /* Receive Register0 */
u32 xSR[4]; /* Status Registers */
u32 xCR[4]; /* Control Registers */
};
+#define IMX_MU_xSR_GIPn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
+#define IMX_MU_xSR_RFn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
+#define IMX_MU_xSR_TEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
+
+/* General Purpose Interrupt Enable */
+#define IMX_MU_xCR_GIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
+/* Receive Interrupt Enable */
+#define IMX_MU_xCR_RIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
+/* Transmit Interrupt Enable */
+#define IMX_MU_xCR_TIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
+/* General Purpose Interrupt Request */
+#define IMX_MU_xCR_GIRn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
+
+
static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
{
return container_of(mbox, struct imx_mu_priv, mbox);
@@ -136,10 +142,10 @@ static int imx_mu_generic_tx(struct imx_mu_priv *priv,
switch (cp->type) {
case IMX_MU_TYPE_TX:
imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
- imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
break;
case IMX_MU_TYPE_TXDB:
- imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
tasklet_schedule(&cp->txdb_tasklet);
break;
default:
@@ -191,7 +197,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
for (; i < msg->hdr.size; i++) {
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
xsr,
- xsr & IMX_MU_xSR_TEn(i % 4),
+ xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % 4),
0, 100);
if (ret) {
dev_err(priv->dev, "Send data index: %d timeout\n", i);
@@ -200,7 +206,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
}
- imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
break;
default:
dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
@@ -218,7 +224,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
int i, ret;
u32 xsr;
- imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(0));
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
*data++ = imx_mu_read(priv, priv->dcfg->xRR);
if (msg.hdr.size > sizeof(msg) / 4) {
@@ -228,7 +234,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
for (i = 1; i < msg.hdr.size; i++) {
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
- xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
+ xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, 100);
if (ret) {
dev_err(priv->dev, "timeout read idx %d\n", i);
return ret;
@@ -236,7 +242,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
}
- imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(0), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
mbox_chan_received_data(cp->chan, (void *)&msg);
return 0;
@@ -260,20 +266,20 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
case IMX_MU_TYPE_TX:
ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
- val &= IMX_MU_xSR_TEn(cp->idx) &
- (ctrl & IMX_MU_xCR_TIEn(cp->idx));
+ val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
+ (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
break;
case IMX_MU_TYPE_RX:
ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
- val &= IMX_MU_xSR_RFn(cp->idx) &
- (ctrl & IMX_MU_xCR_RIEn(cp->idx));
+ val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
+ (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
break;
case IMX_MU_TYPE_RXDB:
ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GCR]);
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
- val &= IMX_MU_xSR_GIPn(cp->idx) &
- (ctrl & IMX_MU_xCR_GIEn(cp->idx));
+ val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
+ (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
break;
default:
break;
@@ -282,13 +288,17 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
if (!val)
return IRQ_NONE;
- if (val == IMX_MU_xSR_TEn(cp->idx)) {
- imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
+ if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
+ (cp->type == IMX_MU_TYPE_TX)) {
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
mbox_chan_txdone(chan, 0);
- } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
+ } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
+ (cp->type == IMX_MU_TYPE_RX)) {
priv->dcfg->rx(priv, cp);
- } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
- imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR[IMX_MU_GSR]);
+ } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
+ (cp->type == IMX_MU_TYPE_RXDB)) {
+ imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
+ priv->dcfg->xSR[IMX_MU_GSR]);
mbox_chan_received_data(chan, NULL);
} else {
dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
@@ -335,10 +345,10 @@ static int imx_mu_startup(struct mbox_chan *chan)
switch (cp->type) {
case IMX_MU_TYPE_RX:
- imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
break;
case IMX_MU_TYPE_RXDB:
- imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIEn(cp->idx), 0);
+ imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
break;
default:
break;
@@ -360,13 +370,13 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
switch (cp->type) {
case IMX_MU_TYPE_TX:
- imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
break;
case IMX_MU_TYPE_RX:
- imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
break;
case IMX_MU_TYPE_RXDB:
- imx_mu_xcr_rmw(priv, IMX_MU_GCR, 0, IMX_MU_xCR_GIEn(cp->idx));
+ imx_mu_xcr_rmw(priv, IMX_MU_GCR, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
break;
default:
break;
@@ -600,12 +610,23 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
.xCR = {0x64, 0x64, 0x64, 0x64},
};
+static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
+ .tx = imx_mu_generic_tx,
+ .rx = imx_mu_generic_rx,
+ .init = imx_mu_init_generic,
+ .type = IMX_MU_V2,
+ .xTR = 0x200,
+ .xRR = 0x280,
+ .xSR = {0xC, 0x118, 0x124, 0x12C},
+ .xCR = {0x8, 0x114, 0x120, 0x128},
+};
+
static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
.tx = imx_mu_scu_tx,
.rx = imx_mu_scu_rx,
.init = imx_mu_init_scu,
- .xTR = 0x0
- .xRR = 0x10
+ .xTR = 0x0,
+ .xRR = 0x10,
.xSR = {0x20, 0x20, 0x20, 0x20},
.xCR = {0x24, 0x24, 0x24, 0x24},
};
@@ -613,6 +634,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
static const struct of_device_id imx_mu_dt_ids[] = {
{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
+ { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
{ },
};
--
2.30.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 3/4] mailbox: imx: add xSR/xCR register array
2021-05-07 10:19 ` Peng Fan (OSS)
@ 2021-05-07 16:08 ` kernel test robot
-1 siblings, 0 replies; 22+ messages in thread
From: kernel test robot @ 2021-05-07 16:08 UTC (permalink / raw)
To: Peng Fan (OSS), jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kbuild-all, clang-built-linux, kernel, festevam, aisheng.dong,
linux-imx, devicetree
[-- Attachment #1: Type: text/plain, Size: 12633 bytes --]
Hi "Peng,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on shawnguo/for-next]
[also build test WARNING on robh/for-next v5.12 next-20210507]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Peng-Fan-OSS/mailbox-imx-add-i-MX8ULP-MU-support/20210507-174948
base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
config: powerpc-randconfig-r023-20210507 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project a3a8a1a15b524d91b5308db68e9d293b34cd88dd)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install powerpc cross compiling tool for clang build
# apt-get install binutils-powerpc-linux-gnu
# https://github.com/0day-ci/linux/commit/356d43252930991aad1353a96361380a7f17f98c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Peng-Fan-OSS/mailbox-imx-add-i-MX8ULP-MU-support/20210507-174948
git checkout 356d43252930991aad1353a96361380a7f17f98c
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
__do_insb
^
arch/powerpc/include/asm/io.h:556:56: note: expanded from macro '__do_insb'
#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from drivers/mailbox/imx-mailbox.c:8:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:10:
In file included from arch/powerpc/include/asm/hardirq.h:6:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:45:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:186:1: note: expanded from here
__do_insw
^
arch/powerpc/include/asm/io.h:557:56: note: expanded from macro '__do_insw'
#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from drivers/mailbox/imx-mailbox.c:8:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:10:
In file included from arch/powerpc/include/asm/hardirq.h:6:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:47:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:188:1: note: expanded from here
__do_insl
^
arch/powerpc/include/asm/io.h:558:56: note: expanded from macro '__do_insl'
#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from drivers/mailbox/imx-mailbox.c:8:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:10:
In file included from arch/powerpc/include/asm/hardirq.h:6:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:49:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:190:1: note: expanded from here
__do_outsb
^
arch/powerpc/include/asm/io.h:559:58: note: expanded from macro '__do_outsb'
#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from drivers/mailbox/imx-mailbox.c:8:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:10:
In file included from arch/powerpc/include/asm/hardirq.h:6:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:51:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:192:1: note: expanded from here
__do_outsw
^
arch/powerpc/include/asm/io.h:560:58: note: expanded from macro '__do_outsw'
#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from drivers/mailbox/imx-mailbox.c:8:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:10:
In file included from arch/powerpc/include/asm/hardirq.h:6:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:53:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:194:1: note: expanded from here
__do_outsl
^
arch/powerpc/include/asm/io.h:561:58: note: expanded from macro '__do_outsl'
#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
~~~~~~~~~~~~~~~~~~~~~^
>> drivers/mailbox/imx-mailbox.c:278:2: warning: variable 'val' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized]
default:
^~~~~~~
drivers/mailbox/imx-mailbox.c:282:7: note: uninitialized use occurs here
if (!val)
^~~
drivers/mailbox/imx-mailbox.c:257:9: note: initialize the variable 'val' to silence this warning
u32 val, ctrl;
^
= 0
drivers/mailbox/imx-mailbox.c:608:2: error: member reference base type 'int' is not a structure or union
.xRR = 0x10
^~~~
drivers/mailbox/imx-mailbox.c:609:2: error: member reference base type 'int' is not a structure or union
.xSR = {0x20, 0x20, 0x20, 0x20},
^~~~
drivers/mailbox/imx-mailbox.c:609:9: error: expected expression
.xSR = {0x20, 0x20, 0x20, 0x20},
^
13 warnings and 3 errors generated.
vim +/val +278 drivers/mailbox/imx-mailbox.c
2bb7005696e224 Oleksij Rempel 2018-08-03 251
2bb7005696e224 Oleksij Rempel 2018-08-03 252 static irqreturn_t imx_mu_isr(int irq, void *p)
2bb7005696e224 Oleksij Rempel 2018-08-03 253 {
2bb7005696e224 Oleksij Rempel 2018-08-03 254 struct mbox_chan *chan = p;
2bb7005696e224 Oleksij Rempel 2018-08-03 255 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
2bb7005696e224 Oleksij Rempel 2018-08-03 256 struct imx_mu_con_priv *cp = chan->con_priv;
63b383575c388f Peng Fan 2020-03-19 257 u32 val, ctrl;
2bb7005696e224 Oleksij Rempel 2018-08-03 258
2bb7005696e224 Oleksij Rempel 2018-08-03 259 switch (cp->type) {
2bb7005696e224 Oleksij Rempel 2018-08-03 260 case IMX_MU_TYPE_TX:
356d4325293099 Peng Fan 2021-05-07 261 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
356d4325293099 Peng Fan 2021-05-07 262 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
2bb7005696e224 Oleksij Rempel 2018-08-03 263 val &= IMX_MU_xSR_TEn(cp->idx) &
2bb7005696e224 Oleksij Rempel 2018-08-03 264 (ctrl & IMX_MU_xCR_TIEn(cp->idx));
2bb7005696e224 Oleksij Rempel 2018-08-03 265 break;
2bb7005696e224 Oleksij Rempel 2018-08-03 266 case IMX_MU_TYPE_RX:
356d4325293099 Peng Fan 2021-05-07 267 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
356d4325293099 Peng Fan 2021-05-07 268 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
2bb7005696e224 Oleksij Rempel 2018-08-03 269 val &= IMX_MU_xSR_RFn(cp->idx) &
2bb7005696e224 Oleksij Rempel 2018-08-03 270 (ctrl & IMX_MU_xCR_RIEn(cp->idx));
2bb7005696e224 Oleksij Rempel 2018-08-03 271 break;
2bb7005696e224 Oleksij Rempel 2018-08-03 272 case IMX_MU_TYPE_RXDB:
356d4325293099 Peng Fan 2021-05-07 273 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GCR]);
356d4325293099 Peng Fan 2021-05-07 274 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
2bb7005696e224 Oleksij Rempel 2018-08-03 275 val &= IMX_MU_xSR_GIPn(cp->idx) &
2bb7005696e224 Oleksij Rempel 2018-08-03 276 (ctrl & IMX_MU_xCR_GIEn(cp->idx));
2bb7005696e224 Oleksij Rempel 2018-08-03 277 break;
2bb7005696e224 Oleksij Rempel 2018-08-03 @278 default:
2bb7005696e224 Oleksij Rempel 2018-08-03 279 break;
2bb7005696e224 Oleksij Rempel 2018-08-03 280 }
2bb7005696e224 Oleksij Rempel 2018-08-03 281
2bb7005696e224 Oleksij Rempel 2018-08-03 282 if (!val)
2bb7005696e224 Oleksij Rempel 2018-08-03 283 return IRQ_NONE;
2bb7005696e224 Oleksij Rempel 2018-08-03 284
2bb7005696e224 Oleksij Rempel 2018-08-03 285 if (val == IMX_MU_xSR_TEn(cp->idx)) {
356d4325293099 Peng Fan 2021-05-07 286 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
2bb7005696e224 Oleksij Rempel 2018-08-03 287 mbox_chan_txdone(chan, 0);
2bb7005696e224 Oleksij Rempel 2018-08-03 288 } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
63b383575c388f Peng Fan 2020-03-19 289 priv->dcfg->rx(priv, cp);
2bb7005696e224 Oleksij Rempel 2018-08-03 290 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
356d4325293099 Peng Fan 2021-05-07 291 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR[IMX_MU_GSR]);
2bb7005696e224 Oleksij Rempel 2018-08-03 292 mbox_chan_received_data(chan, NULL);
2bb7005696e224 Oleksij Rempel 2018-08-03 293 } else {
2bb7005696e224 Oleksij Rempel 2018-08-03 294 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
2bb7005696e224 Oleksij Rempel 2018-08-03 295 return IRQ_NONE;
2bb7005696e224 Oleksij Rempel 2018-08-03 296 }
2bb7005696e224 Oleksij Rempel 2018-08-03 297
2bb7005696e224 Oleksij Rempel 2018-08-03 298 return IRQ_HANDLED;
2bb7005696e224 Oleksij Rempel 2018-08-03 299 }
2bb7005696e224 Oleksij Rempel 2018-08-03 300
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 31392 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/4] mailbox: imx: add xSR/xCR register array
@ 2021-05-07 16:08 ` kernel test robot
0 siblings, 0 replies; 22+ messages in thread
From: kernel test robot @ 2021-05-07 16:08 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 12844 bytes --]
Hi "Peng,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on shawnguo/for-next]
[also build test WARNING on robh/for-next v5.12 next-20210507]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Peng-Fan-OSS/mailbox-imx-add-i-MX8ULP-MU-support/20210507-174948
base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
config: powerpc-randconfig-r023-20210507 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project a3a8a1a15b524d91b5308db68e9d293b34cd88dd)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install powerpc cross compiling tool for clang build
# apt-get install binutils-powerpc-linux-gnu
# https://github.com/0day-ci/linux/commit/356d43252930991aad1353a96361380a7f17f98c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Peng-Fan-OSS/mailbox-imx-add-i-MX8ULP-MU-support/20210507-174948
git checkout 356d43252930991aad1353a96361380a7f17f98c
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
__do_insb
^
arch/powerpc/include/asm/io.h:556:56: note: expanded from macro '__do_insb'
#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from drivers/mailbox/imx-mailbox.c:8:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:10:
In file included from arch/powerpc/include/asm/hardirq.h:6:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:45:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:186:1: note: expanded from here
__do_insw
^
arch/powerpc/include/asm/io.h:557:56: note: expanded from macro '__do_insw'
#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from drivers/mailbox/imx-mailbox.c:8:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:10:
In file included from arch/powerpc/include/asm/hardirq.h:6:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:47:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:188:1: note: expanded from here
__do_insl
^
arch/powerpc/include/asm/io.h:558:56: note: expanded from macro '__do_insl'
#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from drivers/mailbox/imx-mailbox.c:8:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:10:
In file included from arch/powerpc/include/asm/hardirq.h:6:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:49:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:190:1: note: expanded from here
__do_outsb
^
arch/powerpc/include/asm/io.h:559:58: note: expanded from macro '__do_outsb'
#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from drivers/mailbox/imx-mailbox.c:8:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:10:
In file included from arch/powerpc/include/asm/hardirq.h:6:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:51:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:192:1: note: expanded from here
__do_outsw
^
arch/powerpc/include/asm/io.h:560:58: note: expanded from macro '__do_outsw'
#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from drivers/mailbox/imx-mailbox.c:8:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:10:
In file included from arch/powerpc/include/asm/hardirq.h:6:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:53:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:194:1: note: expanded from here
__do_outsl
^
arch/powerpc/include/asm/io.h:561:58: note: expanded from macro '__do_outsl'
#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
~~~~~~~~~~~~~~~~~~~~~^
>> drivers/mailbox/imx-mailbox.c:278:2: warning: variable 'val' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized]
default:
^~~~~~~
drivers/mailbox/imx-mailbox.c:282:7: note: uninitialized use occurs here
if (!val)
^~~
drivers/mailbox/imx-mailbox.c:257:9: note: initialize the variable 'val' to silence this warning
u32 val, ctrl;
^
= 0
drivers/mailbox/imx-mailbox.c:608:2: error: member reference base type 'int' is not a structure or union
.xRR = 0x10
^~~~
drivers/mailbox/imx-mailbox.c:609:2: error: member reference base type 'int' is not a structure or union
.xSR = {0x20, 0x20, 0x20, 0x20},
^~~~
drivers/mailbox/imx-mailbox.c:609:9: error: expected expression
.xSR = {0x20, 0x20, 0x20, 0x20},
^
13 warnings and 3 errors generated.
vim +/val +278 drivers/mailbox/imx-mailbox.c
2bb7005696e224 Oleksij Rempel 2018-08-03 251
2bb7005696e224 Oleksij Rempel 2018-08-03 252 static irqreturn_t imx_mu_isr(int irq, void *p)
2bb7005696e224 Oleksij Rempel 2018-08-03 253 {
2bb7005696e224 Oleksij Rempel 2018-08-03 254 struct mbox_chan *chan = p;
2bb7005696e224 Oleksij Rempel 2018-08-03 255 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
2bb7005696e224 Oleksij Rempel 2018-08-03 256 struct imx_mu_con_priv *cp = chan->con_priv;
63b383575c388f Peng Fan 2020-03-19 257 u32 val, ctrl;
2bb7005696e224 Oleksij Rempel 2018-08-03 258
2bb7005696e224 Oleksij Rempel 2018-08-03 259 switch (cp->type) {
2bb7005696e224 Oleksij Rempel 2018-08-03 260 case IMX_MU_TYPE_TX:
356d4325293099 Peng Fan 2021-05-07 261 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
356d4325293099 Peng Fan 2021-05-07 262 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
2bb7005696e224 Oleksij Rempel 2018-08-03 263 val &= IMX_MU_xSR_TEn(cp->idx) &
2bb7005696e224 Oleksij Rempel 2018-08-03 264 (ctrl & IMX_MU_xCR_TIEn(cp->idx));
2bb7005696e224 Oleksij Rempel 2018-08-03 265 break;
2bb7005696e224 Oleksij Rempel 2018-08-03 266 case IMX_MU_TYPE_RX:
356d4325293099 Peng Fan 2021-05-07 267 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
356d4325293099 Peng Fan 2021-05-07 268 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
2bb7005696e224 Oleksij Rempel 2018-08-03 269 val &= IMX_MU_xSR_RFn(cp->idx) &
2bb7005696e224 Oleksij Rempel 2018-08-03 270 (ctrl & IMX_MU_xCR_RIEn(cp->idx));
2bb7005696e224 Oleksij Rempel 2018-08-03 271 break;
2bb7005696e224 Oleksij Rempel 2018-08-03 272 case IMX_MU_TYPE_RXDB:
356d4325293099 Peng Fan 2021-05-07 273 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GCR]);
356d4325293099 Peng Fan 2021-05-07 274 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
2bb7005696e224 Oleksij Rempel 2018-08-03 275 val &= IMX_MU_xSR_GIPn(cp->idx) &
2bb7005696e224 Oleksij Rempel 2018-08-03 276 (ctrl & IMX_MU_xCR_GIEn(cp->idx));
2bb7005696e224 Oleksij Rempel 2018-08-03 277 break;
2bb7005696e224 Oleksij Rempel 2018-08-03 @278 default:
2bb7005696e224 Oleksij Rempel 2018-08-03 279 break;
2bb7005696e224 Oleksij Rempel 2018-08-03 280 }
2bb7005696e224 Oleksij Rempel 2018-08-03 281
2bb7005696e224 Oleksij Rempel 2018-08-03 282 if (!val)
2bb7005696e224 Oleksij Rempel 2018-08-03 283 return IRQ_NONE;
2bb7005696e224 Oleksij Rempel 2018-08-03 284
2bb7005696e224 Oleksij Rempel 2018-08-03 285 if (val == IMX_MU_xSR_TEn(cp->idx)) {
356d4325293099 Peng Fan 2021-05-07 286 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
2bb7005696e224 Oleksij Rempel 2018-08-03 287 mbox_chan_txdone(chan, 0);
2bb7005696e224 Oleksij Rempel 2018-08-03 288 } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
63b383575c388f Peng Fan 2020-03-19 289 priv->dcfg->rx(priv, cp);
2bb7005696e224 Oleksij Rempel 2018-08-03 290 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
356d4325293099 Peng Fan 2021-05-07 291 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR[IMX_MU_GSR]);
2bb7005696e224 Oleksij Rempel 2018-08-03 292 mbox_chan_received_data(chan, NULL);
2bb7005696e224 Oleksij Rempel 2018-08-03 293 } else {
2bb7005696e224 Oleksij Rempel 2018-08-03 294 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
2bb7005696e224 Oleksij Rempel 2018-08-03 295 return IRQ_NONE;
2bb7005696e224 Oleksij Rempel 2018-08-03 296 }
2bb7005696e224 Oleksij Rempel 2018-08-03 297
2bb7005696e224 Oleksij Rempel 2018-08-03 298 return IRQ_HANDLED;
2bb7005696e224 Oleksij Rempel 2018-08-03 299 }
2bb7005696e224 Oleksij Rempel 2018-08-03 300
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 31392 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/4] mailbox: imx: add xSR/xCR register array
2021-05-07 16:08 ` kernel test robot
@ 2021-05-10 1:21 ` Peng Fan
-1 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-10 1:21 UTC (permalink / raw)
To: kernel test robot, jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kbuild-all, clang-built-linux, kernel, festevam, aisheng.dong,
linux-imx, devicetree
On 2021/5/8 0:08, kernel test robot wrote:
> Hi "Peng,
>
> Thank you for the patch! Perhaps something to improve:
>
> [auto build test WARNING on shawnguo/for-next]
> [also build test WARNING on robh/for-next v5.12 next-20210507]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url: https://github.com/0day-ci/linux/commits/Peng-Fan-OSS/mailbox-imx-add-i-MX8ULP-MU-support/20210507-174948
> base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
> config: powerpc-randconfig-r023-20210507 (attached as .config)
> compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project a3a8a1a15b524d91b5308db68e9d293b34cd88dd)
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install powerpc cross compiling tool for clang build
> # apt-get install binutils-powerpc-linux-gnu
> # https://github.com/0day-ci/linux/commit/356d43252930991aad1353a96361380a7f17f98c
> git remote add linux-review https://github.com/0day-ci/linux
> git fetch --no-tags linux-review Peng-Fan-OSS/mailbox-imx-add-i-MX8ULP-MU-support/20210507-174948
> git checkout 356d43252930991aad1353a96361380a7f17f98c
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=powerpc
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>):
>
> __do_insb
> ^
> arch/powerpc/include/asm/io.h:556:56: note: expanded from macro '__do_insb'
> #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
> ~~~~~~~~~~~~~~~~~~~~~^
> In file included from drivers/mailbox/imx-mailbox.c:8:
> In file included from include/linux/interrupt.h:11:
> In file included from include/linux/hardirq.h:10:
> In file included from arch/powerpc/include/asm/hardirq.h:6:
> In file included from include/linux/irq.h:20:
> In file included from include/linux/io.h:13:
> In file included from arch/powerpc/include/asm/io.h:619:
> arch/powerpc/include/asm/io-defs.h:45:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c),
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
> __do_##name al;
This should be common powerpc issue?
Regards,
Peng.
\
> ^~~~~~~~~~~~~~
> <scratch space>:186:1: note: expanded from here
> __do_insw
> ^
> arch/powerpc/include/asm/io.h:557:56: note: expanded from macro '__do_insw'
> #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
> ~~~~~~~~~~~~~~~~~~~~~^
> In file included from drivers/mailbox/imx-mailbox.c:8:
> In file included from include/linux/interrupt.h:11:
> In file included from include/linux/hardirq.h:10:
> In file included from arch/powerpc/include/asm/hardirq.h:6:
> In file included from include/linux/irq.h:20:
> In file included from include/linux/io.h:13:
> In file included from arch/powerpc/include/asm/io.h:619:
> arch/powerpc/include/asm/io-defs.h:47:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c),
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
> __do_##name al; \
> ^~~~~~~~~~~~~~
> <scratch space>:188:1: note: expanded from here
> __do_insl
> ^
> arch/powerpc/include/asm/io.h:558:56: note: expanded from macro '__do_insl'
> #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
> ~~~~~~~~~~~~~~~~~~~~~^
> In file included from drivers/mailbox/imx-mailbox.c:8:
> In file included from include/linux/interrupt.h:11:
> In file included from include/linux/hardirq.h:10:
> In file included from arch/powerpc/include/asm/hardirq.h:6:
> In file included from include/linux/irq.h:20:
> In file included from include/linux/io.h:13:
> In file included from arch/powerpc/include/asm/io.h:619:
> arch/powerpc/include/asm/io-defs.h:49:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c),
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
> __do_##name al; \
> ^~~~~~~~~~~~~~
> <scratch space>:190:1: note: expanded from here
> __do_outsb
> ^
> arch/powerpc/include/asm/io.h:559:58: note: expanded from macro '__do_outsb'
> #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
> ~~~~~~~~~~~~~~~~~~~~~^
> In file included from drivers/mailbox/imx-mailbox.c:8:
> In file included from include/linux/interrupt.h:11:
> In file included from include/linux/hardirq.h:10:
> In file included from arch/powerpc/include/asm/hardirq.h:6:
> In file included from include/linux/irq.h:20:
> In file included from include/linux/io.h:13:
> In file included from arch/powerpc/include/asm/io.h:619:
> arch/powerpc/include/asm/io-defs.h:51:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c),
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
> __do_##name al; \
> ^~~~~~~~~~~~~~
> <scratch space>:192:1: note: expanded from here
> __do_outsw
> ^
> arch/powerpc/include/asm/io.h:560:58: note: expanded from macro '__do_outsw'
> #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
> ~~~~~~~~~~~~~~~~~~~~~^
> In file included from drivers/mailbox/imx-mailbox.c:8:
> In file included from include/linux/interrupt.h:11:
> In file included from include/linux/hardirq.h:10:
> In file included from arch/powerpc/include/asm/hardirq.h:6:
> In file included from include/linux/irq.h:20:
> In file included from include/linux/io.h:13:
> In file included from arch/powerpc/include/asm/io.h:619:
> arch/powerpc/include/asm/io-defs.h:53:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c),
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
> __do_##name al; \
> ^~~~~~~~~~~~~~
> <scratch space>:194:1: note: expanded from here
> __do_outsl
> ^
> arch/powerpc/include/asm/io.h:561:58: note: expanded from macro '__do_outsl'
> #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
> ~~~~~~~~~~~~~~~~~~~~~^
>>> drivers/mailbox/imx-mailbox.c:278:2: warning: variable 'val' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized]
> default:
> ^~~~~~~
> drivers/mailbox/imx-mailbox.c:282:7: note: uninitialized use occurs here
> if (!val)
> ^~~
> drivers/mailbox/imx-mailbox.c:257:9: note: initialize the variable 'val' to silence this warning
> u32 val, ctrl;
> ^
> = 0
> drivers/mailbox/imx-mailbox.c:608:2: error: member reference base type 'int' is not a structure or union
> .xRR = 0x10
> ^~~~
> drivers/mailbox/imx-mailbox.c:609:2: error: member reference base type 'int' is not a structure or union
> .xSR = {0x20, 0x20, 0x20, 0x20},
> ^~~~
> drivers/mailbox/imx-mailbox.c:609:9: error: expected expression
> .xSR = {0x20, 0x20, 0x20, 0x20},
> ^
> 13 warnings and 3 errors generated.
>
>
> vim +/val +278 drivers/mailbox/imx-mailbox.c
>
> 2bb7005696e224 Oleksij Rempel 2018-08-03 251
> 2bb7005696e224 Oleksij Rempel 2018-08-03 252 static irqreturn_t imx_mu_isr(int irq, void *p)
> 2bb7005696e224 Oleksij Rempel 2018-08-03 253 {
> 2bb7005696e224 Oleksij Rempel 2018-08-03 254 struct mbox_chan *chan = p;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 255 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 256 struct imx_mu_con_priv *cp = chan->con_priv;
> 63b383575c388f Peng Fan 2020-03-19 257 u32 val, ctrl;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 258
> 2bb7005696e224 Oleksij Rempel 2018-08-03 259 switch (cp->type) {
> 2bb7005696e224 Oleksij Rempel 2018-08-03 260 case IMX_MU_TYPE_TX:
> 356d4325293099 Peng Fan 2021-05-07 261 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
> 356d4325293099 Peng Fan 2021-05-07 262 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 263 val &= IMX_MU_xSR_TEn(cp->idx) &
> 2bb7005696e224 Oleksij Rempel 2018-08-03 264 (ctrl & IMX_MU_xCR_TIEn(cp->idx));
> 2bb7005696e224 Oleksij Rempel 2018-08-03 265 break;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 266 case IMX_MU_TYPE_RX:
> 356d4325293099 Peng Fan 2021-05-07 267 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
> 356d4325293099 Peng Fan 2021-05-07 268 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 269 val &= IMX_MU_xSR_RFn(cp->idx) &
> 2bb7005696e224 Oleksij Rempel 2018-08-03 270 (ctrl & IMX_MU_xCR_RIEn(cp->idx));
> 2bb7005696e224 Oleksij Rempel 2018-08-03 271 break;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 272 case IMX_MU_TYPE_RXDB:
> 356d4325293099 Peng Fan 2021-05-07 273 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GCR]);
> 356d4325293099 Peng Fan 2021-05-07 274 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 275 val &= IMX_MU_xSR_GIPn(cp->idx) &
> 2bb7005696e224 Oleksij Rempel 2018-08-03 276 (ctrl & IMX_MU_xCR_GIEn(cp->idx));
> 2bb7005696e224 Oleksij Rempel 2018-08-03 277 break;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 @278 default:
> 2bb7005696e224 Oleksij Rempel 2018-08-03 279 break;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 280 }
> 2bb7005696e224 Oleksij Rempel 2018-08-03 281
> 2bb7005696e224 Oleksij Rempel 2018-08-03 282 if (!val)
> 2bb7005696e224 Oleksij Rempel 2018-08-03 283 return IRQ_NONE;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 284
> 2bb7005696e224 Oleksij Rempel 2018-08-03 285 if (val == IMX_MU_xSR_TEn(cp->idx)) {
> 356d4325293099 Peng Fan 2021-05-07 286 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
> 2bb7005696e224 Oleksij Rempel 2018-08-03 287 mbox_chan_txdone(chan, 0);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 288 } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
> 63b383575c388f Peng Fan 2020-03-19 289 priv->dcfg->rx(priv, cp);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 290 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
> 356d4325293099 Peng Fan 2021-05-07 291 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR[IMX_MU_GSR]);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 292 mbox_chan_received_data(chan, NULL);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 293 } else {
> 2bb7005696e224 Oleksij Rempel 2018-08-03 294 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
> 2bb7005696e224 Oleksij Rempel 2018-08-03 295 return IRQ_NONE;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 296 }
> 2bb7005696e224 Oleksij Rempel 2018-08-03 297
> 2bb7005696e224 Oleksij Rempel 2018-08-03 298 return IRQ_HANDLED;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 299 }
> 2bb7005696e224 Oleksij Rempel 2018-08-03 300
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/4] mailbox: imx: add xSR/xCR register array
@ 2021-05-10 1:21 ` Peng Fan
0 siblings, 0 replies; 22+ messages in thread
From: Peng Fan @ 2021-05-10 1:21 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 13490 bytes --]
On 2021/5/8 0:08, kernel test robot wrote:
> Hi "Peng,
>
> Thank you for the patch! Perhaps something to improve:
>
> [auto build test WARNING on shawnguo/for-next]
> [also build test WARNING on robh/for-next v5.12 next-20210507]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url: https://github.com/0day-ci/linux/commits/Peng-Fan-OSS/mailbox-imx-add-i-MX8ULP-MU-support/20210507-174948
> base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
> config: powerpc-randconfig-r023-20210507 (attached as .config)
> compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project a3a8a1a15b524d91b5308db68e9d293b34cd88dd)
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install powerpc cross compiling tool for clang build
> # apt-get install binutils-powerpc-linux-gnu
> # https://github.com/0day-ci/linux/commit/356d43252930991aad1353a96361380a7f17f98c
> git remote add linux-review https://github.com/0day-ci/linux
> git fetch --no-tags linux-review Peng-Fan-OSS/mailbox-imx-add-i-MX8ULP-MU-support/20210507-174948
> git checkout 356d43252930991aad1353a96361380a7f17f98c
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=powerpc
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>):
>
> __do_insb
> ^
> arch/powerpc/include/asm/io.h:556:56: note: expanded from macro '__do_insb'
> #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
> ~~~~~~~~~~~~~~~~~~~~~^
> In file included from drivers/mailbox/imx-mailbox.c:8:
> In file included from include/linux/interrupt.h:11:
> In file included from include/linux/hardirq.h:10:
> In file included from arch/powerpc/include/asm/hardirq.h:6:
> In file included from include/linux/irq.h:20:
> In file included from include/linux/io.h:13:
> In file included from arch/powerpc/include/asm/io.h:619:
> arch/powerpc/include/asm/io-defs.h:45:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c),
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
> __do_##name al;
This should be common powerpc issue?
Regards,
Peng.
\
> ^~~~~~~~~~~~~~
> <scratch space>:186:1: note: expanded from here
> __do_insw
> ^
> arch/powerpc/include/asm/io.h:557:56: note: expanded from macro '__do_insw'
> #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
> ~~~~~~~~~~~~~~~~~~~~~^
> In file included from drivers/mailbox/imx-mailbox.c:8:
> In file included from include/linux/interrupt.h:11:
> In file included from include/linux/hardirq.h:10:
> In file included from arch/powerpc/include/asm/hardirq.h:6:
> In file included from include/linux/irq.h:20:
> In file included from include/linux/io.h:13:
> In file included from arch/powerpc/include/asm/io.h:619:
> arch/powerpc/include/asm/io-defs.h:47:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c),
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
> __do_##name al; \
> ^~~~~~~~~~~~~~
> <scratch space>:188:1: note: expanded from here
> __do_insl
> ^
> arch/powerpc/include/asm/io.h:558:56: note: expanded from macro '__do_insl'
> #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
> ~~~~~~~~~~~~~~~~~~~~~^
> In file included from drivers/mailbox/imx-mailbox.c:8:
> In file included from include/linux/interrupt.h:11:
> In file included from include/linux/hardirq.h:10:
> In file included from arch/powerpc/include/asm/hardirq.h:6:
> In file included from include/linux/irq.h:20:
> In file included from include/linux/io.h:13:
> In file included from arch/powerpc/include/asm/io.h:619:
> arch/powerpc/include/asm/io-defs.h:49:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c),
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
> __do_##name al; \
> ^~~~~~~~~~~~~~
> <scratch space>:190:1: note: expanded from here
> __do_outsb
> ^
> arch/powerpc/include/asm/io.h:559:58: note: expanded from macro '__do_outsb'
> #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
> ~~~~~~~~~~~~~~~~~~~~~^
> In file included from drivers/mailbox/imx-mailbox.c:8:
> In file included from include/linux/interrupt.h:11:
> In file included from include/linux/hardirq.h:10:
> In file included from arch/powerpc/include/asm/hardirq.h:6:
> In file included from include/linux/irq.h:20:
> In file included from include/linux/io.h:13:
> In file included from arch/powerpc/include/asm/io.h:619:
> arch/powerpc/include/asm/io-defs.h:51:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c),
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
> __do_##name al; \
> ^~~~~~~~~~~~~~
> <scratch space>:192:1: note: expanded from here
> __do_outsw
> ^
> arch/powerpc/include/asm/io.h:560:58: note: expanded from macro '__do_outsw'
> #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
> ~~~~~~~~~~~~~~~~~~~~~^
> In file included from drivers/mailbox/imx-mailbox.c:8:
> In file included from include/linux/interrupt.h:11:
> In file included from include/linux/hardirq.h:10:
> In file included from arch/powerpc/include/asm/hardirq.h:6:
> In file included from include/linux/irq.h:20:
> In file included from include/linux/io.h:13:
> In file included from arch/powerpc/include/asm/io.h:619:
> arch/powerpc/include/asm/io-defs.h:53:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c),
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
> __do_##name al; \
> ^~~~~~~~~~~~~~
> <scratch space>:194:1: note: expanded from here
> __do_outsl
> ^
> arch/powerpc/include/asm/io.h:561:58: note: expanded from macro '__do_outsl'
> #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
> ~~~~~~~~~~~~~~~~~~~~~^
>>> drivers/mailbox/imx-mailbox.c:278:2: warning: variable 'val' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized]
> default:
> ^~~~~~~
> drivers/mailbox/imx-mailbox.c:282:7: note: uninitialized use occurs here
> if (!val)
> ^~~
> drivers/mailbox/imx-mailbox.c:257:9: note: initialize the variable 'val' to silence this warning
> u32 val, ctrl;
> ^
> = 0
> drivers/mailbox/imx-mailbox.c:608:2: error: member reference base type 'int' is not a structure or union
> .xRR = 0x10
> ^~~~
> drivers/mailbox/imx-mailbox.c:609:2: error: member reference base type 'int' is not a structure or union
> .xSR = {0x20, 0x20, 0x20, 0x20},
> ^~~~
> drivers/mailbox/imx-mailbox.c:609:9: error: expected expression
> .xSR = {0x20, 0x20, 0x20, 0x20},
> ^
> 13 warnings and 3 errors generated.
>
>
> vim +/val +278 drivers/mailbox/imx-mailbox.c
>
> 2bb7005696e224 Oleksij Rempel 2018-08-03 251
> 2bb7005696e224 Oleksij Rempel 2018-08-03 252 static irqreturn_t imx_mu_isr(int irq, void *p)
> 2bb7005696e224 Oleksij Rempel 2018-08-03 253 {
> 2bb7005696e224 Oleksij Rempel 2018-08-03 254 struct mbox_chan *chan = p;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 255 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 256 struct imx_mu_con_priv *cp = chan->con_priv;
> 63b383575c388f Peng Fan 2020-03-19 257 u32 val, ctrl;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 258
> 2bb7005696e224 Oleksij Rempel 2018-08-03 259 switch (cp->type) {
> 2bb7005696e224 Oleksij Rempel 2018-08-03 260 case IMX_MU_TYPE_TX:
> 356d4325293099 Peng Fan 2021-05-07 261 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
> 356d4325293099 Peng Fan 2021-05-07 262 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 263 val &= IMX_MU_xSR_TEn(cp->idx) &
> 2bb7005696e224 Oleksij Rempel 2018-08-03 264 (ctrl & IMX_MU_xCR_TIEn(cp->idx));
> 2bb7005696e224 Oleksij Rempel 2018-08-03 265 break;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 266 case IMX_MU_TYPE_RX:
> 356d4325293099 Peng Fan 2021-05-07 267 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
> 356d4325293099 Peng Fan 2021-05-07 268 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 269 val &= IMX_MU_xSR_RFn(cp->idx) &
> 2bb7005696e224 Oleksij Rempel 2018-08-03 270 (ctrl & IMX_MU_xCR_RIEn(cp->idx));
> 2bb7005696e224 Oleksij Rempel 2018-08-03 271 break;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 272 case IMX_MU_TYPE_RXDB:
> 356d4325293099 Peng Fan 2021-05-07 273 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GCR]);
> 356d4325293099 Peng Fan 2021-05-07 274 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 275 val &= IMX_MU_xSR_GIPn(cp->idx) &
> 2bb7005696e224 Oleksij Rempel 2018-08-03 276 (ctrl & IMX_MU_xCR_GIEn(cp->idx));
> 2bb7005696e224 Oleksij Rempel 2018-08-03 277 break;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 @278 default:
> 2bb7005696e224 Oleksij Rempel 2018-08-03 279 break;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 280 }
> 2bb7005696e224 Oleksij Rempel 2018-08-03 281
> 2bb7005696e224 Oleksij Rempel 2018-08-03 282 if (!val)
> 2bb7005696e224 Oleksij Rempel 2018-08-03 283 return IRQ_NONE;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 284
> 2bb7005696e224 Oleksij Rempel 2018-08-03 285 if (val == IMX_MU_xSR_TEn(cp->idx)) {
> 356d4325293099 Peng Fan 2021-05-07 286 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
> 2bb7005696e224 Oleksij Rempel 2018-08-03 287 mbox_chan_txdone(chan, 0);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 288 } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
> 63b383575c388f Peng Fan 2020-03-19 289 priv->dcfg->rx(priv, cp);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 290 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
> 356d4325293099 Peng Fan 2021-05-07 291 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR[IMX_MU_GSR]);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 292 mbox_chan_received_data(chan, NULL);
> 2bb7005696e224 Oleksij Rempel 2018-08-03 293 } else {
> 2bb7005696e224 Oleksij Rempel 2018-08-03 294 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
> 2bb7005696e224 Oleksij Rempel 2018-08-03 295 return IRQ_NONE;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 296 }
> 2bb7005696e224 Oleksij Rempel 2018-08-03 297
> 2bb7005696e224 Oleksij Rempel 2018-08-03 298 return IRQ_HANDLED;
> 2bb7005696e224 Oleksij Rempel 2018-08-03 299 }
> 2bb7005696e224 Oleksij Rempel 2018-08-03 300
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/4] dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
2021-05-07 10:19 ` Peng Fan (OSS)
@ 2021-05-10 15:49 ` Rob Herring
-1 siblings, 0 replies; 22+ messages in thread
From: Rob Herring @ 2021-05-10 15:49 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Peng Fan, devicetree, festevam, aisheng.dong, s.hauer, robh+dt,
linux-imx, kernel, linux-kernel, linux-arm-kernel,
jassisinghbrar, o.rempel, shawnguo
On Fri, 07 May 2021 18:19:23 +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> The register layout and bits definition of i.MX8ULP MU is different
> compared with others, let's add the compatible for the new MU.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/4] dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
@ 2021-05-10 15:49 ` Rob Herring
0 siblings, 0 replies; 22+ messages in thread
From: Rob Herring @ 2021-05-10 15:49 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Peng Fan, devicetree, festevam, aisheng.dong, s.hauer, robh+dt,
linux-imx, kernel, linux-kernel, linux-arm-kernel,
jassisinghbrar, o.rempel, shawnguo
On Fri, 07 May 2021 18:19:23 +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> The register layout and bits definition of i.MX8ULP MU is different
> compared with others, let's add the compatible for the new MU.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/4] mailbox: imx: add i.MX8ULP MU support
2021-05-07 10:19 ` Peng Fan (OSS)
@ 2021-05-26 6:06 ` Peng Fan (OSS)
-1 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-26 6:06 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kernel, festevam, aisheng.dong, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
Hi Jassi, Shawn
On 2021/5/7 18:19, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> i.MX8ULP generic MU is a different IP compared with previous i.MX chips.
> It has different register layout and bit position, but the register name
> and bit definitions are almost same with previous i.MX MU.
>
> So we extend the current imx-mailbox driver to support i.MX8ULP.
Gentle ping.. Except dt-bindings patch get A-b from Rob,no comments.
Is it ok for you to pick up this patchset?
Thanks,
Peng.
>
> Peng Fan (4):
> dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
> mailbox: imx: replace the xTR/xRR array with single register
> mailbox: imx: add xSR/xCR register array
> mailbox: imx-mailbox: support i.MX8ULP MU
>
> .../devicetree/bindings/mailbox/fsl,mu.yaml | 1 +
> drivers/mailbox/imx-mailbox.c | 196 +++++++++++-------
> 2 files changed, 123 insertions(+), 74 deletions(-)
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/4] mailbox: imx: add i.MX8ULP MU support
@ 2021-05-26 6:06 ` Peng Fan (OSS)
0 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-26 6:06 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, shawnguo, s.hauer, o.rempel
Cc: kernel, festevam, aisheng.dong, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
Hi Jassi, Shawn
On 2021/5/7 18:19, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> i.MX8ULP generic MU is a different IP compared with previous i.MX chips.
> It has different register layout and bit position, but the register name
> and bit definitions are almost same with previous i.MX MU.
>
> So we extend the current imx-mailbox driver to support i.MX8ULP.
Gentle ping.. Except dt-bindings patch get A-b from Rob,no comments.
Is it ok for you to pick up this patchset?
Thanks,
Peng.
>
> Peng Fan (4):
> dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
> mailbox: imx: replace the xTR/xRR array with single register
> mailbox: imx: add xSR/xCR register array
> mailbox: imx-mailbox: support i.MX8ULP MU
>
> .../devicetree/bindings/mailbox/fsl,mu.yaml | 1 +
> drivers/mailbox/imx-mailbox.c | 196 +++++++++++-------
> 2 files changed, 123 insertions(+), 74 deletions(-)
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/4] mailbox: imx: replace the xTR/xRR array with single register
2021-05-07 10:19 ` Peng Fan (OSS)
@ 2021-05-26 6:58 ` Daniel Baluta
-1 siblings, 0 replies; 22+ messages in thread
From: Daniel Baluta @ 2021-05-26 6:58 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Jassi Brar, Rob Herring, Shawn Guo, Sascha Hauer, Oleksij Rempel,
Pengutronix Kernel Team, Fabio Estevam, Aisheng Dong,
dl-linux-imx, Devicetree List, linux-arm-kernel,
Linux Kernel Mailing List, Peng Fan
On Fri, May 7, 2021 at 3:33 PM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Peng Fan <peng.fan@nxp.com>
>
> The xTR/xRR registers are using 4 bytes stride and continuous.
> Considering we will support more TR and RR registers, use base + idx * 4
> method to calculate register address, not hardcoding in driver.
>
Peng, this means that for imx8ul the Tx registers are not continuous
right? Please make this clear in
the commit message.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/mailbox/imx-mailbox.c | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
> index 2543c7b6948b..bd7758c32a80 100644
> --- a/drivers/mailbox/imx-mailbox.c
> +++ b/drivers/mailbox/imx-mailbox.c
> @@ -76,8 +76,8 @@ struct imx_mu_dcfg {
> int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
> int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
> void (*init)(struct imx_mu_priv *priv);
> - u32 xTR[4]; /* Transmit Registers */
> - u32 xRR[4]; /* Receive Registers */
> + u32 xTR; /* Transmit Register0 */
> + u32 xRR; /* Receive Register0 */
> u32 xSR; /* Status Register */
> u32 xCR; /* Control Register */
> };
> @@ -120,7 +120,7 @@ static int imx_mu_generic_tx(struct imx_mu_priv *priv,
>
> switch (cp->type) {
> case IMX_MU_TYPE_TX:
> - imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
> + imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
> imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
> break;
> case IMX_MU_TYPE_TXDB:
> @@ -140,7 +140,7 @@ static int imx_mu_generic_rx(struct imx_mu_priv *priv,
> {
> u32 dat;
>
> - dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
> + dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
> mbox_chan_received_data(cp->chan, (void *)&dat);
>
> return 0;
> @@ -172,7 +172,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
> }
>
> for (i = 0; i < 4 && i < msg->hdr.size; i++)
> - imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
> + imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
> for (; i < msg->hdr.size; i++) {
> ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
> xsr,
> @@ -182,7 +182,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
> dev_err(priv->dev, "Send data index: %d timeout\n", i);
> return ret;
> }
> - imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
> + imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
> }
>
> imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
> @@ -204,7 +204,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
> u32 xsr;
>
> imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
> - *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
> + *data++ = imx_mu_read(priv, priv->dcfg->xRR);
>
> if (msg.hdr.size > sizeof(msg) / 4) {
> dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
> @@ -218,7 +218,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
> dev_err(priv->dev, "timeout read idx %d\n", i);
> return ret;
> }
> - *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
> + *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
> }
>
> imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
> @@ -564,8 +564,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
> .tx = imx_mu_generic_tx,
> .rx = imx_mu_generic_rx,
> .init = imx_mu_init_generic,
> - .xTR = {0x0, 0x4, 0x8, 0xc},
> - .xRR = {0x10, 0x14, 0x18, 0x1c},
> + .xTR = 0x0,
> + .xRR = 0x10,
> .xSR = 0x20,
> .xCR = 0x24,
> };
> @@ -574,8 +574,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
> .tx = imx_mu_generic_tx,
> .rx = imx_mu_generic_rx,
> .init = imx_mu_init_generic,
> - .xTR = {0x20, 0x24, 0x28, 0x2c},
> - .xRR = {0x40, 0x44, 0x48, 0x4c},
> + .xTR = 0x20,
> + .xRR = 0x40,
> .xSR = 0x60,
> .xCR = 0x64,
> };
> @@ -584,8 +584,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
> .tx = imx_mu_scu_tx,
> .rx = imx_mu_scu_rx,
> .init = imx_mu_init_scu,
> - .xTR = {0x0, 0x4, 0x8, 0xc},
> - .xRR = {0x10, 0x14, 0x18, 0x1c},
> + .xTR = 0x0
> + .xRR = 0x10
> .xSR = 0x20,
> .xCR = 0x24,
> };
> --
> 2.30.0
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/4] mailbox: imx: replace the xTR/xRR array with single register
@ 2021-05-26 6:58 ` Daniel Baluta
0 siblings, 0 replies; 22+ messages in thread
From: Daniel Baluta @ 2021-05-26 6:58 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Jassi Brar, Rob Herring, Shawn Guo, Sascha Hauer, Oleksij Rempel,
Pengutronix Kernel Team, Fabio Estevam, Aisheng Dong,
dl-linux-imx, Devicetree List, linux-arm-kernel,
Linux Kernel Mailing List, Peng Fan
On Fri, May 7, 2021 at 3:33 PM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Peng Fan <peng.fan@nxp.com>
>
> The xTR/xRR registers are using 4 bytes stride and continuous.
> Considering we will support more TR and RR registers, use base + idx * 4
> method to calculate register address, not hardcoding in driver.
>
Peng, this means that for imx8ul the Tx registers are not continuous
right? Please make this clear in
the commit message.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/mailbox/imx-mailbox.c | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
> index 2543c7b6948b..bd7758c32a80 100644
> --- a/drivers/mailbox/imx-mailbox.c
> +++ b/drivers/mailbox/imx-mailbox.c
> @@ -76,8 +76,8 @@ struct imx_mu_dcfg {
> int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
> int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
> void (*init)(struct imx_mu_priv *priv);
> - u32 xTR[4]; /* Transmit Registers */
> - u32 xRR[4]; /* Receive Registers */
> + u32 xTR; /* Transmit Register0 */
> + u32 xRR; /* Receive Register0 */
> u32 xSR; /* Status Register */
> u32 xCR; /* Control Register */
> };
> @@ -120,7 +120,7 @@ static int imx_mu_generic_tx(struct imx_mu_priv *priv,
>
> switch (cp->type) {
> case IMX_MU_TYPE_TX:
> - imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
> + imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
> imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
> break;
> case IMX_MU_TYPE_TXDB:
> @@ -140,7 +140,7 @@ static int imx_mu_generic_rx(struct imx_mu_priv *priv,
> {
> u32 dat;
>
> - dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
> + dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
> mbox_chan_received_data(cp->chan, (void *)&dat);
>
> return 0;
> @@ -172,7 +172,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
> }
>
> for (i = 0; i < 4 && i < msg->hdr.size; i++)
> - imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
> + imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
> for (; i < msg->hdr.size; i++) {
> ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
> xsr,
> @@ -182,7 +182,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
> dev_err(priv->dev, "Send data index: %d timeout\n", i);
> return ret;
> }
> - imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
> + imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
> }
>
> imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
> @@ -204,7 +204,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
> u32 xsr;
>
> imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
> - *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
> + *data++ = imx_mu_read(priv, priv->dcfg->xRR);
>
> if (msg.hdr.size > sizeof(msg) / 4) {
> dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
> @@ -218,7 +218,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
> dev_err(priv->dev, "timeout read idx %d\n", i);
> return ret;
> }
> - *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
> + *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
> }
>
> imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
> @@ -564,8 +564,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
> .tx = imx_mu_generic_tx,
> .rx = imx_mu_generic_rx,
> .init = imx_mu_init_generic,
> - .xTR = {0x0, 0x4, 0x8, 0xc},
> - .xRR = {0x10, 0x14, 0x18, 0x1c},
> + .xTR = 0x0,
> + .xRR = 0x10,
> .xSR = 0x20,
> .xCR = 0x24,
> };
> @@ -574,8 +574,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
> .tx = imx_mu_generic_tx,
> .rx = imx_mu_generic_rx,
> .init = imx_mu_init_generic,
> - .xTR = {0x20, 0x24, 0x28, 0x2c},
> - .xRR = {0x40, 0x44, 0x48, 0x4c},
> + .xTR = 0x20,
> + .xRR = 0x40,
> .xSR = 0x60,
> .xCR = 0x64,
> };
> @@ -584,8 +584,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
> .tx = imx_mu_scu_tx,
> .rx = imx_mu_scu_rx,
> .init = imx_mu_init_scu,
> - .xTR = {0x0, 0x4, 0x8, 0xc},
> - .xRR = {0x10, 0x14, 0x18, 0x1c},
> + .xTR = 0x0
> + .xRR = 0x10
> .xSR = 0x20,
> .xCR = 0x24,
> };
> --
> 2.30.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/4] mailbox: imx: replace the xTR/xRR array with single register
2021-05-26 6:58 ` Daniel Baluta
@ 2021-05-27 0:36 ` Peng Fan (OSS)
-1 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-27 0:36 UTC (permalink / raw)
To: Daniel Baluta
Cc: Jassi Brar, Rob Herring, Shawn Guo, Sascha Hauer, Oleksij Rempel,
Pengutronix Kernel Team, Fabio Estevam, Aisheng Dong,
dl-linux-imx, Devicetree List, linux-arm-kernel,
Linux Kernel Mailing List, Peng Fan
On 2021/5/26 14:58, Daniel Baluta wrote:
> On Fri, May 7, 2021 at 3:33 PM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>>
>> From: Peng Fan <peng.fan@nxp.com>
>>
>> The xTR/xRR registers are using 4 bytes stride and continuous.
>> Considering we will support more TR and RR registers, use base + idx * 4
>> method to calculate register address, not hardcoding in driver.
>>
> Peng, this means that for imx8ul the Tx registers are not continuous
> right? Please make this clear in
> the commit message.
It is continuous, it support more than 4 registers, so we use idx * 4 to
calculate the address, not hardcoding in an array as before.
Thanks,
Peng.
>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>> drivers/mailbox/imx-mailbox.c | 28 ++++++++++++++--------------
>> 1 file changed, 14 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
>> index 2543c7b6948b..bd7758c32a80 100644
>> --- a/drivers/mailbox/imx-mailbox.c
>> +++ b/drivers/mailbox/imx-mailbox.c
>> @@ -76,8 +76,8 @@ struct imx_mu_dcfg {
>> int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
>> int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
>> void (*init)(struct imx_mu_priv *priv);
>> - u32 xTR[4]; /* Transmit Registers */
>> - u32 xRR[4]; /* Receive Registers */
>> + u32 xTR; /* Transmit Register0 */
>> + u32 xRR; /* Receive Register0 */
>> u32 xSR; /* Status Register */
>> u32 xCR; /* Control Register */
>> };
>> @@ -120,7 +120,7 @@ static int imx_mu_generic_tx(struct imx_mu_priv *priv,
>>
>> switch (cp->type) {
>> case IMX_MU_TYPE_TX:
>> - imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
>> + imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
>> imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
>> break;
>> case IMX_MU_TYPE_TXDB:
>> @@ -140,7 +140,7 @@ static int imx_mu_generic_rx(struct imx_mu_priv *priv,
>> {
>> u32 dat;
>>
>> - dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
>> + dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
>> mbox_chan_received_data(cp->chan, (void *)&dat);
>>
>> return 0;
>> @@ -172,7 +172,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
>> }
>>
>> for (i = 0; i < 4 && i < msg->hdr.size; i++)
>> - imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
>> + imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
>> for (; i < msg->hdr.size; i++) {
>> ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
>> xsr,
>> @@ -182,7 +182,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
>> dev_err(priv->dev, "Send data index: %d timeout\n", i);
>> return ret;
>> }
>> - imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
>> + imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
>> }
>>
>> imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
>> @@ -204,7 +204,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
>> u32 xsr;
>>
>> imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
>> - *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
>> + *data++ = imx_mu_read(priv, priv->dcfg->xRR);
>>
>> if (msg.hdr.size > sizeof(msg) / 4) {
>> dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
>> @@ -218,7 +218,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
>> dev_err(priv->dev, "timeout read idx %d\n", i);
>> return ret;
>> }
>> - *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
>> + *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
>> }
>>
>> imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
>> @@ -564,8 +564,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
>> .tx = imx_mu_generic_tx,
>> .rx = imx_mu_generic_rx,
>> .init = imx_mu_init_generic,
>> - .xTR = {0x0, 0x4, 0x8, 0xc},
>> - .xRR = {0x10, 0x14, 0x18, 0x1c},
>> + .xTR = 0x0,
>> + .xRR = 0x10,
>> .xSR = 0x20,
>> .xCR = 0x24,
>> };
>> @@ -574,8 +574,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
>> .tx = imx_mu_generic_tx,
>> .rx = imx_mu_generic_rx,
>> .init = imx_mu_init_generic,
>> - .xTR = {0x20, 0x24, 0x28, 0x2c},
>> - .xRR = {0x40, 0x44, 0x48, 0x4c},
>> + .xTR = 0x20,
>> + .xRR = 0x40,
>> .xSR = 0x60,
>> .xCR = 0x64,
>> };
>> @@ -584,8 +584,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
>> .tx = imx_mu_scu_tx,
>> .rx = imx_mu_scu_rx,
>> .init = imx_mu_init_scu,
>> - .xTR = {0x0, 0x4, 0x8, 0xc},
>> - .xRR = {0x10, 0x14, 0x18, 0x1c},
>> + .xTR = 0x0
>> + .xRR = 0x10
>> .xSR = 0x20,
>> .xCR = 0x24,
>> };
>> --
>> 2.30.0
>>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/4] mailbox: imx: replace the xTR/xRR array with single register
@ 2021-05-27 0:36 ` Peng Fan (OSS)
0 siblings, 0 replies; 22+ messages in thread
From: Peng Fan (OSS) @ 2021-05-27 0:36 UTC (permalink / raw)
To: Daniel Baluta
Cc: Jassi Brar, Rob Herring, Shawn Guo, Sascha Hauer, Oleksij Rempel,
Pengutronix Kernel Team, Fabio Estevam, Aisheng Dong,
dl-linux-imx, Devicetree List, linux-arm-kernel,
Linux Kernel Mailing List, Peng Fan
On 2021/5/26 14:58, Daniel Baluta wrote:
> On Fri, May 7, 2021 at 3:33 PM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>>
>> From: Peng Fan <peng.fan@nxp.com>
>>
>> The xTR/xRR registers are using 4 bytes stride and continuous.
>> Considering we will support more TR and RR registers, use base + idx * 4
>> method to calculate register address, not hardcoding in driver.
>>
> Peng, this means that for imx8ul the Tx registers are not continuous
> right? Please make this clear in
> the commit message.
It is continuous, it support more than 4 registers, so we use idx * 4 to
calculate the address, not hardcoding in an array as before.
Thanks,
Peng.
>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>> drivers/mailbox/imx-mailbox.c | 28 ++++++++++++++--------------
>> 1 file changed, 14 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
>> index 2543c7b6948b..bd7758c32a80 100644
>> --- a/drivers/mailbox/imx-mailbox.c
>> +++ b/drivers/mailbox/imx-mailbox.c
>> @@ -76,8 +76,8 @@ struct imx_mu_dcfg {
>> int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
>> int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
>> void (*init)(struct imx_mu_priv *priv);
>> - u32 xTR[4]; /* Transmit Registers */
>> - u32 xRR[4]; /* Receive Registers */
>> + u32 xTR; /* Transmit Register0 */
>> + u32 xRR; /* Receive Register0 */
>> u32 xSR; /* Status Register */
>> u32 xCR; /* Control Register */
>> };
>> @@ -120,7 +120,7 @@ static int imx_mu_generic_tx(struct imx_mu_priv *priv,
>>
>> switch (cp->type) {
>> case IMX_MU_TYPE_TX:
>> - imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
>> + imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
>> imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
>> break;
>> case IMX_MU_TYPE_TXDB:
>> @@ -140,7 +140,7 @@ static int imx_mu_generic_rx(struct imx_mu_priv *priv,
>> {
>> u32 dat;
>>
>> - dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
>> + dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
>> mbox_chan_received_data(cp->chan, (void *)&dat);
>>
>> return 0;
>> @@ -172,7 +172,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
>> }
>>
>> for (i = 0; i < 4 && i < msg->hdr.size; i++)
>> - imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
>> + imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
>> for (; i < msg->hdr.size; i++) {
>> ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
>> xsr,
>> @@ -182,7 +182,7 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
>> dev_err(priv->dev, "Send data index: %d timeout\n", i);
>> return ret;
>> }
>> - imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
>> + imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
>> }
>>
>> imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
>> @@ -204,7 +204,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
>> u32 xsr;
>>
>> imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
>> - *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
>> + *data++ = imx_mu_read(priv, priv->dcfg->xRR);
>>
>> if (msg.hdr.size > sizeof(msg) / 4) {
>> dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
>> @@ -218,7 +218,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
>> dev_err(priv->dev, "timeout read idx %d\n", i);
>> return ret;
>> }
>> - *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
>> + *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
>> }
>>
>> imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
>> @@ -564,8 +564,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
>> .tx = imx_mu_generic_tx,
>> .rx = imx_mu_generic_rx,
>> .init = imx_mu_init_generic,
>> - .xTR = {0x0, 0x4, 0x8, 0xc},
>> - .xRR = {0x10, 0x14, 0x18, 0x1c},
>> + .xTR = 0x0,
>> + .xRR = 0x10,
>> .xSR = 0x20,
>> .xCR = 0x24,
>> };
>> @@ -574,8 +574,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
>> .tx = imx_mu_generic_tx,
>> .rx = imx_mu_generic_rx,
>> .init = imx_mu_init_generic,
>> - .xTR = {0x20, 0x24, 0x28, 0x2c},
>> - .xRR = {0x40, 0x44, 0x48, 0x4c},
>> + .xTR = 0x20,
>> + .xRR = 0x40,
>> .xSR = 0x60,
>> .xCR = 0x64,
>> };
>> @@ -584,8 +584,8 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
>> .tx = imx_mu_scu_tx,
>> .rx = imx_mu_scu_rx,
>> .init = imx_mu_init_scu,
>> - .xTR = {0x0, 0x4, 0x8, 0xc},
>> - .xRR = {0x10, 0x14, 0x18, 0x1c},
>> + .xTR = 0x0
>> + .xRR = 0x10
>> .xSR = 0x20,
>> .xCR = 0x24,
>> };
>> --
>> 2.30.0
>>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2021-05-27 0:38 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-07 10:19 [PATCH 0/4] mailbox: imx: add i.MX8ULP MU support Peng Fan (OSS)
2021-05-07 10:19 ` Peng Fan (OSS)
2021-05-07 10:19 ` [PATCH 1/4] dt-bindings: mailbox: imx-mu: " Peng Fan (OSS)
2021-05-07 10:19 ` Peng Fan (OSS)
2021-05-10 15:49 ` Rob Herring
2021-05-10 15:49 ` Rob Herring
2021-05-07 10:19 ` [PATCH 2/4] mailbox: imx: replace the xTR/xRR array with single register Peng Fan (OSS)
2021-05-07 10:19 ` Peng Fan (OSS)
2021-05-26 6:58 ` Daniel Baluta
2021-05-26 6:58 ` Daniel Baluta
2021-05-27 0:36 ` Peng Fan (OSS)
2021-05-27 0:36 ` Peng Fan (OSS)
2021-05-07 10:19 ` [PATCH 3/4] mailbox: imx: add xSR/xCR register array Peng Fan (OSS)
2021-05-07 10:19 ` Peng Fan (OSS)
2021-05-07 16:08 ` kernel test robot
2021-05-07 16:08 ` kernel test robot
2021-05-10 1:21 ` Peng Fan (OSS)
2021-05-10 1:21 ` Peng Fan
2021-05-07 10:19 ` [PATCH 4/4] mailbox: imx-mailbox: support i.MX8ULP MU Peng Fan (OSS)
2021-05-07 10:19 ` Peng Fan (OSS)
2021-05-26 6:06 ` [PATCH 0/4] mailbox: imx: add i.MX8ULP MU support Peng Fan (OSS)
2021-05-26 6:06 ` Peng Fan (OSS)
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