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* [PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz
@ 2021-08-09 12:13 Marek Vasut
  2021-09-20  7:39 ` Alexandre TORGUE
  0 siblings, 1 reply; 5+ messages in thread
From: Marek Vasut @ 2021-08-09 12:13 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Marek Vasut, Alexandre Torgue, Patrice Chotard, Patrick Delaunay,
	linux-stm32

The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
which causes additional signal delay. At 108 MHz, this delay triggers
a sporadic issue where the first bit of RX data is not received by the
QSPI controller.

There are two options of addressing this problem, either by using the
DLYB block to compensate the extra delay, or by reducing the QSPI bus
clock frequency. The former requires calibration and that is overly
complex, so opt for the second option.

Fixes: 76045bc457104 ("ARM: dts: stm32: Add QSPI NOR on AV96")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
---
 arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
index 2b0ac605549d7..44ecc47085871 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
@@ -202,7 +202,7 @@ flash0: flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-rx-bus-width = <4>;
-		spi-max-frequency = <108000000>;
+		spi-max-frequency = <50000000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 	};
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz
  2021-08-09 12:13 [PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz Marek Vasut
@ 2021-09-20  7:39 ` Alexandre TORGUE
  0 siblings, 0 replies; 5+ messages in thread
From: Alexandre TORGUE @ 2021-09-20  7:39 UTC (permalink / raw)
  To: Marek Vasut, linux-arm-kernel
  Cc: Patrice Chotard, Patrick Delaunay, linux-stm32

Hi Marek

On 8/9/21 2:13 PM, Marek Vasut wrote:
> The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
> which causes additional signal delay. At 108 MHz, this delay triggers
> a sporadic issue where the first bit of RX data is not received by the
> QSPI controller.
> 
> There are two options of addressing this problem, either by using the
> DLYB block to compensate the extra delay, or by reducing the QSPI bus
> clock frequency. The former requires calibration and that is overly
> complex, so opt for the second option.
> 
> Fixes: 76045bc457104 ("ARM: dts: stm32: Add QSPI NOR on AV96")
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
> Cc: Patrice Chotard <patrice.chotard@foss.st.com>
> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
> Cc: linux-stm32@st-md-mailman.stormreply.com
> To: linux-arm-kernel@lists.infradead.org
> ---
>   arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
> index 2b0ac605549d7..44ecc47085871 100644
> --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
> +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
> @@ -202,7 +202,7 @@ flash0: flash@0 {
>   		compatible = "jedec,spi-nor";
>   		reg = <0>;
>   		spi-rx-bus-width = <4>;
> -		spi-max-frequency = <108000000>;
> +		spi-max-frequency = <50000000>;
>   		#address-cells = <1>;
>   		#size-cells = <1>;
>   	};
> 

Applied on stm32-next.

Thanks
Alex

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz
  2021-08-09 12:33 ` Patrice CHOTARD
@ 2021-08-16 11:29   ` Patrice CHOTARD
  0 siblings, 0 replies; 5+ messages in thread
From: Patrice CHOTARD @ 2021-08-16 11:29 UTC (permalink / raw)
  To: Marek Vasut, u-boot; +Cc: Patrick Delaunay

Hi Marek

On 8/9/21 2:33 PM, Patrice CHOTARD wrote:
> Hi Marek
> 
> On 8/9/21 2:06 PM, Marek Vasut wrote:
>> The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
>> which causes additional signal delay. At 108 MHz, this delay triggers
>> a sporadic issue where the first bit of RX data is not received by the
>> QSPI controller.
>>
>> There are two options of addressing this problem, either by using the
>> DLYB block to compensate the extra delay, or by reducing the QSPI bus
>> clock frequency. The former requires calibration and that is overly
>> complex for SPL, so opt for the second option. This incurs 20ms delay
>> during boot, when SPL loads U-Boot to DRAM.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> Cc: Patrice Chotard <patrice.chotard@foss.st.com>
>> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
>> ---
>>  arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi
>> index 64299df8166..94cf80dbede 100644
>> --- a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi
>> +++ b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi
>> @@ -198,7 +198,7 @@
>>  		compatible = "jedec,spi-nor";
>>  		reg = <0>;
>>  		spi-rx-bus-width = <4>;
>> -		spi-max-frequency = <108000000>;
>> +		spi-max-frequency = <50000000>;
>>  		#address-cells = <1>;
>>  		#size-cells = <1>;
>>  	};
>>
> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
> 
> Thanks
> Patrice
> 
Applied to u-boot-stm/master

Thanks
Patrice

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz
  2021-08-09 12:06 Marek Vasut
@ 2021-08-09 12:33 ` Patrice CHOTARD
  2021-08-16 11:29   ` Patrice CHOTARD
  0 siblings, 1 reply; 5+ messages in thread
From: Patrice CHOTARD @ 2021-08-09 12:33 UTC (permalink / raw)
  To: Marek Vasut, u-boot; +Cc: Patrick Delaunay

Hi Marek

On 8/9/21 2:06 PM, Marek Vasut wrote:
> The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
> which causes additional signal delay. At 108 MHz, this delay triggers
> a sporadic issue where the first bit of RX data is not received by the
> QSPI controller.
> 
> There are two options of addressing this problem, either by using the
> DLYB block to compensate the extra delay, or by reducing the QSPI bus
> clock frequency. The former requires calibration and that is overly
> complex for SPL, so opt for the second option. This incurs 20ms delay
> during boot, when SPL loads U-Boot to DRAM.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrice Chotard <patrice.chotard@foss.st.com>
> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
> ---
>  arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi
> index 64299df8166..94cf80dbede 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi
> @@ -198,7 +198,7 @@
>  		compatible = "jedec,spi-nor";
>  		reg = <0>;
>  		spi-rx-bus-width = <4>;
> -		spi-max-frequency = <108000000>;
> +		spi-max-frequency = <50000000>;
>  		#address-cells = <1>;
>  		#size-cells = <1>;
>  	};
> 
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

Thanks
Patrice

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz
@ 2021-08-09 12:06 Marek Vasut
  2021-08-09 12:33 ` Patrice CHOTARD
  0 siblings, 1 reply; 5+ messages in thread
From: Marek Vasut @ 2021-08-09 12:06 UTC (permalink / raw)
  To: u-boot; +Cc: Marek Vasut, Patrice Chotard, Patrick Delaunay

The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
which causes additional signal delay. At 108 MHz, this delay triggers
a sporadic issue where the first bit of RX data is not received by the
QSPI controller.

There are two options of addressing this problem, either by using the
DLYB block to compensate the extra delay, or by reducing the QSPI bus
clock frequency. The former requires calibration and that is overly
complex for SPL, so opt for the second option. This incurs 20ms delay
during boot, when SPL loads U-Boot to DRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
---
 arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi
index 64299df8166..94cf80dbede 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi
@@ -198,7 +198,7 @@
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-rx-bus-width = <4>;
-		spi-max-frequency = <108000000>;
+		spi-max-frequency = <50000000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 	};
-- 
2.30.2


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2021-09-20  7:41 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2021-08-09 12:13 [PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz Marek Vasut
2021-09-20  7:39 ` Alexandre TORGUE
  -- strict thread matches above, loose matches on Subject: below --
2021-08-09 12:06 Marek Vasut
2021-08-09 12:33 ` Patrice CHOTARD
2021-08-16 11:29   ` Patrice CHOTARD

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