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Mon, 20 Sep 2021 09:39:31 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A748D10002A; Mon, 20 Sep 2021 09:39:30 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 8B98E2128A0; Mon, 20 Sep 2021 09:39:30 +0200 (CEST) Received: from lmecxl0912.lme.st.com (10.75.127.46) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 20 Sep 2021 09:39:30 +0200 Subject: Re: [PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz To: Marek Vasut , CC: Patrice Chotard , Patrick Delaunay , References: <20210809121324.155219-1-marex@denx.de> From: Alexandre TORGUE Message-ID: Date: Mon, 20 Sep 2021 09:39:29 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210809121324.155219-1-marex@denx.de> Content-Language: en-US X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG1NODE3.st.com (10.75.127.3) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-20_03,2021-09-17_02,2020-04-07_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210920_003933_849892_E8A830BF X-CRM114-Status: GOOD ( 26.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marek On 8/9/21 2:13 PM, Marek Vasut wrote: > The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM, > which causes additional signal delay. At 108 MHz, this delay triggers > a sporadic issue where the first bit of RX data is not received by the > QSPI controller. > > There are two options of addressing this problem, either by using the > DLYB block to compensate the extra delay, or by reducing the QSPI bus > clock frequency. The former requires calibration and that is overly > complex, so opt for the second option. > > Fixes: 76045bc457104 ("ARM: dts: stm32: Add QSPI NOR on AV96") > Signed-off-by: Marek Vasut > Cc: Alexandre Torgue > Cc: Patrice Chotard > Cc: Patrick Delaunay > Cc: linux-stm32@st-md-mailman.stormreply.com > To: linux-arm-kernel@lists.infradead.org > --- > arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi > index 2b0ac605549d7..44ecc47085871 100644 > --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi > +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi > @@ -202,7 +202,7 @@ flash0: flash@0 { > compatible = "jedec,spi-nor"; > reg = <0>; > spi-rx-bus-width = <4>; > - spi-max-frequency = <108000000>; > + spi-max-frequency = <50000000>; > #address-cells = <1>; > #size-cells = <1>; > }; > Applied on stm32-next. Thanks Alex _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel