From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5220AC43461 for ; Wed, 16 Sep 2020 15:56:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0CC00208E4 for ; Wed, 16 Sep 2020 15:56:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600271802; bh=jHIPUklgKCiY93bGZ11uk5ol4lLn0bboEPgtNpIBuek=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=auNhq/k88DUKKqi5X6RuIr2FTAMwaQnNwgTXT8nlGHuTR07dvw+IzSxs/gnbPtQ1x p0g09wPu8w3U2wuR9b0kdAFR+X+YGCBwUQb6DQNJKTBoq4XwP0SzcFLWcOtMq8b8sm Qw5LL25RNpRbpuPC4rXJLXFkDG5z4zTE4+T67wTI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726399AbgIPP4j (ORCPT ); Wed, 16 Sep 2020 11:56:39 -0400 Received: from mail.kernel.org ([198.145.29.99]:57126 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726159AbgIPPzc (ORCPT ); Wed, 16 Sep 2020 11:55:32 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5A3992245C; Wed, 16 Sep 2020 15:55:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600271729; bh=jHIPUklgKCiY93bGZ11uk5ol4lLn0bboEPgtNpIBuek=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=SP7hjKBFbreEF5j0JqqCm6dgGzkCZ6Z8/m0mxvCDNN1/cbtAF9ObulHJiwCMV86Hq W4bbaVBKCYDiCcxDnfUX2m1zpe2+31NLa1zEKxN/Q4H+b3qW9BPxQxBYEJ3l/kRPZn L9URZo+ExYN2Fp0zUgEZJoHwVjURzWoxQxFy0Tv8= Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1kIZmJ-00CNI7-FE; Wed, 16 Sep 2020 16:55:27 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Date: Wed, 16 Sep 2020 16:55:27 +0100 From: Marc Zyngier To: Jon Hunter Cc: Sumit Garg , linus.walleij@linaro.org, Florian Fainelli , Russell King , Jason Cooper , Saravana Kannan , Andrew Lunn , Catalin Marinas , Gregory Clement , Bartlomiej Zolnierkiewicz , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Will Deacon , 'Linux Samsung SOC' , linux-tegra , Thomas Gleixner , kernel-team@android.com, Valentin Schneider , linux-arm-kernel@lists.infradead.org, Marek Szyprowski Subject: Re: [PATCH v3 08/16] irqchip/gic: Configure SGIs as standard interrupts In-Reply-To: References: <20200901144324.1071694-1-maz@kernel.org> <20200901144324.1071694-9-maz@kernel.org> <933bc43e-3cd7-10ec-b9ec-58afaa619fb7@nvidia.com> <3378cd07b92e87a24f1db75f708424ee@kernel.org> User-Agent: Roundcube Webmail/1.4.8 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: jonathanh@nvidia.com, sumit.garg@linaro.org, linus.walleij@linaro.org, f.fainelli@gmail.com, linux@arm.linux.org.uk, jason@lakedaemon.net, saravanak@google.com, andrew@lunn.ch, catalin.marinas@arm.com, gregory.clement@bootlin.com, b.zolnierkie@samsung.com, linux-kernel@vger.kernel.org, krzk@kernel.org, will@kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, tglx@linutronix.de, kernel-team@android.com, Valentin.Schneider@arm.com, linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On 2020-09-16 16:46, Jon Hunter wrote: > On 16/09/2020 16:10, Marc Zyngier wrote: >> Hi Jon, >> >> +Linus, who is facing a similar issue. >> >> On 2020-09-16 15:16, Jon Hunter wrote: >>> Hi Marc, >>> >>> On 14/09/2020 14:06, Marek Szyprowski wrote: >>>> Hi Marc, >>>> >>>> On 01.09.2020 16:43, Marc Zyngier wrote: >>>>> Change the way we deal with GIC SGIs by turning them into proper >>>>> IRQs, and calling into the arch code to register the interrupt >>>>> range >>>>> instead of a callback. >>>>> >>>>> Reviewed-by: Valentin Schneider >>>>> Signed-off-by: Marc Zyngier >>>> This patch landed in linux next-20200914 as commit ac063232d4b0 >>>> ("irqchip/gic: Configure SGIs as standard interrupts"). Sadly it >>>> breaks >>>> booting of all Samsung Exynos 4210/4412 based boards (dual/quad ARM >>>> Cortex A9 based). Here are the last lines from the bootlog: >>> >>> I am observing the same thing on several Tegra boards (both arm and >>> arm64). Bisect is pointing to this commit. Reverting this alone does >>> not >>> appear to be enough to fix the issue. >> >> Right, I am just massively by the GICv3 spec, and failed to remember >> that ye olde GIC exposes the source CPU in AIR *and* wants it back, >> while >> newer GICs deal with that transparently. >> >> Can you try the patch below and let me know? > > Yes will do. > >> @@ -365,14 +354,13 @@ static void __exception_irq_entry >> gic_handle_irq(struct pt_regs *regs) >>              smp_rmb(); >> >>              /* >> -             * Samsung's funky GIC encodes the source CPU in >> -             * GICC_IAR, leading to the deactivation to fail if >> -             * not written back as is to GICC_EOI.  Stash the >> -             * INTID away for gic_eoi_irq() to write back. >> -             * This only works because we don't nest SGIs... >> +             * The GIC encodes the source CPU in GICC_IAR, >> +             * leading to the deactivation to fail if not >> +             * written back as is to GICC_EOI.  Stash the INTID >> +             * away for gic_eoi_irq() to write back.  This only >> +             * works because we don't nest SGIs... >>               */ >> -            if (is_frankengic()) >> -                set_sgi_intid(irqstat); >> +            this_cpu_write(sgi_intid, intid); > > I assume that it should be irqstat here and not intid? Indeed. As you can tell, I haven't even tried to compile it, sorry about that. M. -- Jazz is not dead. It just smells funny... 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Wed, 16 Sep 2020 16:55:27 +0100 MIME-Version: 1.0 Date: Wed, 16 Sep 2020 16:55:27 +0100 From: Marc Zyngier To: Jon Hunter Subject: Re: [PATCH v3 08/16] irqchip/gic: Configure SGIs as standard interrupts In-Reply-To: References: <20200901144324.1071694-1-maz@kernel.org> <20200901144324.1071694-9-maz@kernel.org> <933bc43e-3cd7-10ec-b9ec-58afaa619fb7@nvidia.com> <3378cd07b92e87a24f1db75f708424ee@kernel.org> User-Agent: Roundcube Webmail/1.4.8 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: jonathanh@nvidia.com, sumit.garg@linaro.org, linus.walleij@linaro.org, f.fainelli@gmail.com, linux@arm.linux.org.uk, jason@lakedaemon.net, saravanak@google.com, andrew@lunn.ch, catalin.marinas@arm.com, gregory.clement@bootlin.com, b.zolnierkie@samsung.com, linux-kernel@vger.kernel.org, krzk@kernel.org, will@kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, tglx@linutronix.de, kernel-team@android.com, Valentin.Schneider@arm.com, linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200916_115530_586811_0F27487B X-CRM114-Status: GOOD ( 20.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sumit Garg , kernel-team@android.com, Florian Fainelli , Russell King , Jason Cooper , Saravana Kannan , Andrew Lunn , Catalin Marinas , linus.walleij@linaro.org, Bartlomiej Zolnierkiewicz , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Valentin Schneider , 'Linux Samsung SOC' , linux-tegra , Thomas Gleixner , Will Deacon , Gregory Clement , linux-arm-kernel@lists.infradead.org, Marek Szyprowski Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gMjAyMC0wOS0xNiAxNjo0NiwgSm9uIEh1bnRlciB3cm90ZToKPiBPbiAxNi8wOS8yMDIwIDE2 OjEwLCBNYXJjIFp5bmdpZXIgd3JvdGU6Cj4+IEhpIEpvbiwKPj4gCj4+ICtMaW51cywgd2hvIGlz IGZhY2luZyBhIHNpbWlsYXIgaXNzdWUuCj4+IAo+PiBPbiAyMDIwLTA5LTE2IDE1OjE2LCBKb24g SHVudGVyIHdyb3RlOgo+Pj4gSGkgTWFyYywKPj4+IAo+Pj4gT24gMTQvMDkvMjAyMCAxNDowNiwg TWFyZWsgU3p5cHJvd3NraSB3cm90ZToKPj4+PiBIaSBNYXJjLAo+Pj4+IAo+Pj4+IE9uIDAxLjA5 LjIwMjAgMTY6NDMsIE1hcmMgWnluZ2llciB3cm90ZToKPj4+Pj4gQ2hhbmdlIHRoZSB3YXkgd2Ug ZGVhbCB3aXRoIEdJQyBTR0lzIGJ5IHR1cm5pbmcgdGhlbSBpbnRvIHByb3Blcgo+Pj4+PiBJUlFz LCBhbmQgY2FsbGluZyBpbnRvIHRoZSBhcmNoIGNvZGUgdG8gcmVnaXN0ZXIgdGhlIGludGVycnVw dCAKPj4+Pj4gcmFuZ2UKPj4+Pj4gaW5zdGVhZCBvZiBhIGNhbGxiYWNrLgo+Pj4+PiAKPj4+Pj4g UmV2aWV3ZWQtYnk6IFZhbGVudGluIFNjaG5laWRlciA8dmFsZW50aW4uc2NobmVpZGVyQGFybS5j b20+Cj4+Pj4+IFNpZ25lZC1vZmYtYnk6IE1hcmMgWnluZ2llciA8bWF6QGtlcm5lbC5vcmc+Cj4+ Pj4gVGhpcyBwYXRjaCBsYW5kZWQgaW4gbGludXggbmV4dC0yMDIwMDkxNCBhcyBjb21taXQgYWMw NjMyMzJkNGIwCj4+Pj4gKCJpcnFjaGlwL2dpYzogQ29uZmlndXJlIFNHSXMgYXMgc3RhbmRhcmQg aW50ZXJydXB0cyIpLiBTYWRseSBpdCAKPj4+PiBicmVha3MKPj4+PiBib290aW5nIG9mIGFsbCBT YW1zdW5nIEV4eW5vcyA0MjEwLzQ0MTIgYmFzZWQgYm9hcmRzIChkdWFsL3F1YWQgQVJNCj4+Pj4g Q29ydGV4IEE5IGJhc2VkKS4gSGVyZSBhcmUgdGhlIGxhc3QgbGluZXMgZnJvbSB0aGUgYm9vdGxv ZzoKPj4+IAo+Pj4gSSBhbSBvYnNlcnZpbmcgdGhlIHNhbWUgdGhpbmcgb24gc2V2ZXJhbCBUZWdy YSBib2FyZHMgKGJvdGggYXJtIGFuZAo+Pj4gYXJtNjQpLiBCaXNlY3QgaXMgcG9pbnRpbmcgdG8g dGhpcyBjb21taXQuIFJldmVydGluZyB0aGlzIGFsb25lIGRvZXMgCj4+PiBub3QKPj4+IGFwcGVh ciB0byBiZSBlbm91Z2ggdG8gZml4IHRoZSBpc3N1ZS4KPj4gCj4+IFJpZ2h0LCBJIGFtIGp1c3Qg bWFzc2l2ZWx5IGJ5IHRoZSBHSUN2MyBzcGVjLCBhbmQgZmFpbGVkIHRvIHJlbWVtYmVyCj4+IHRo YXQgeWUgb2xkZSBHSUMgZXhwb3NlcyB0aGUgc291cmNlIENQVSBpbiBBSVIgKmFuZCogd2FudHMg aXQgYmFjaywgCj4+IHdoaWxlCj4+IG5ld2VyIEdJQ3MgZGVhbCB3aXRoIHRoYXQgdHJhbnNwYXJl bnRseS4KPj4gCj4+IENhbiB5b3UgdHJ5IHRoZSBwYXRjaCBiZWxvdyBhbmQgbGV0IG1lIGtub3c/ Cj4gCj4gWWVzIHdpbGwgZG8uCj4gCj4+IEBAIC0zNjUsMTQgKzM1NCwxMyBAQCBzdGF0aWMgdm9p ZCBfX2V4Y2VwdGlvbl9pcnFfZW50cnkKPj4gZ2ljX2hhbmRsZV9pcnEoc3RydWN0IHB0X3JlZ3Mg KnJlZ3MpCj4+IMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBzbXBfcm1iKCk7Cj4+IAo+PiDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqAgLyoKPj4gLcKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAqIFNh bXN1bmcncyBmdW5reSBHSUMgZW5jb2RlcyB0aGUgc291cmNlIENQVSBpbgo+PiAtwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgICogR0lDQ19JQVIsIGxlYWRpbmcgdG8gdGhlIGRlYWN0aXZhdGlvbiB0 byBmYWlsIGlmCj4+IC3CoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgKiBub3Qgd3JpdHRlbiBiYWNr IGFzIGlzIHRvIEdJQ0NfRU9JLsKgIFN0YXNoIHRoZQo+PiAtwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgICogSU5USUQgYXdheSBmb3IgZ2ljX2VvaV9pcnEoKSB0byB3cml0ZSBiYWNrLgo+PiAtwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgICogVGhpcyBvbmx5IHdvcmtzIGJlY2F1c2Ugd2UgZG9uJ3Qg bmVzdCBTR0lzLi4uCj4+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgKiBUaGUgR0lDIGVuY29k ZXMgdGhlIHNvdXJjZSBDUFUgaW4gR0lDQ19JQVIsCj4+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqAgKiBsZWFkaW5nIHRvIHRoZSBkZWFjdGl2YXRpb24gdG8gZmFpbCBpZiBub3QKPj4gK8KgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoCAqIHdyaXR0ZW4gYmFjayBhcyBpcyB0byBHSUNDX0VPSS7CoCBT dGFzaCB0aGUgSU5USUQKPj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAqIGF3YXkgZm9yIGdp Y19lb2lfaXJxKCkgdG8gd3JpdGUgYmFjay7CoCBUaGlzIG9ubHkKPj4gK8KgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoCAqIHdvcmtzIGJlY2F1c2Ugd2UgZG9uJ3QgbmVzdCBTR0lzLi4uCj4+IMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgICovCj4+IC3CoMKgwqDCoMKgwqDCoMKgwqDCoMKgIGlmIChp c19mcmFua2VuZ2ljKCkpCj4+IC3CoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgc2V0X3Nn aV9pbnRpZChpcnFzdGF0KTsKPj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqAgdGhpc19jcHVfd3Jp dGUoc2dpX2ludGlkLCBpbnRpZCk7Cj4gCj4gSSBhc3N1bWUgdGhhdCBpdCBzaG91bGQgYmUgaXJx c3RhdCBoZXJlIGFuZCBub3QgaW50aWQ/CgpJbmRlZWQuIEFzIHlvdSBjYW4gdGVsbCwgSSBoYXZl bid0IGV2ZW4gdHJpZWQgdG8gY29tcGlsZSBpdCwgc29ycnkgYWJvdXQgCnRoYXQuCgogICAgICAg ICBNLgotLSAKSmF6eiBpcyBub3QgZGVhZC4gSXQganVzdCBzbWVsbHMgZnVubnkuLi4KCl9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LWFybS1rZXJu ZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRw Oi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwK