From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6035C433E1 for ; Wed, 26 Aug 2020 11:42:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AF8F620707 for ; Wed, 26 Aug 2020 11:42:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="XD+94RGF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729035AbgHZLmf (ORCPT ); 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Wed, 26 Aug 2020 06:35:46 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 26 Aug 2020 06:35:46 -0500 Received: from [10.250.68.181] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07QBZkES010512; Wed, 26 Aug 2020 06:35:46 -0500 Subject: Re: [PATCH v2] net: dp83869: Fix RGMII internal delay configuration To: Daniel Gorsulowski , CC: , , , References: <20200826050014.428639-1-daniel.gorsulowski@esd.eu> From: Dan Murphy Message-ID: Date: Wed, 26 Aug 2020 06:35:45 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200826050014.428639-1-daniel.gorsulowski@esd.eu> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hello On 8/26/20 12:00 AM, Daniel Gorsulowski wrote: > The RGMII control register at 0x32 indicates the states for the bits > RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows: > > RGMII Transmit/Receive Clock Delay > 0x0 = RGMII transmit clock is shifted with respect to transmit/receive data. > 0x1 = RGMII transmit clock is aligned with respect to transmit/receive data. > > This commit fixes the inversed behavior of these bits > > Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration") > Signed-off-by: Daniel Gorsulowski > --- > v2: fixed indentation and commit style > > drivers/net/phy/dp83869.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c > index 58103152c601..6b98d74b5102 100644 > --- a/drivers/net/phy/dp83869.c > +++ b/drivers/net/phy/dp83869.c > @@ -427,18 +427,18 @@ static int dp83869_config_init(struct phy_device *phydev) > return ret; > > val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); > - val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | > - DP83869_RGMII_RX_CLK_DELAY_EN); > + val |= (DP83869_RGMII_TX_CLK_DELAY_EN | > + DP83869_RGMII_RX_CLK_DELAY_EN); > > if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) > - val |= (DP83869_RGMII_TX_CLK_DELAY_EN | > - DP83869_RGMII_RX_CLK_DELAY_EN); > + val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | > + DP83869_RGMII_RX_CLK_DELAY_EN); > > if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) > - val |= DP83869_RGMII_TX_CLK_DELAY_EN; > + val &= ~DP83869_RGMII_TX_CLK_DELAY_EN; > > if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) > - val |= DP83869_RGMII_RX_CLK_DELAY_EN; > + val &= ~DP83869_RGMII_RX_CLK_DELAY_EN; > > ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, > val); With the exception on bot knowing what net tree this goes to via the subject Acked-by: Dan Murphy