From: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file
Date: Mon, 27 Nov 2017 13:54:02 -0500 [thread overview]
Message-ID: <a831909b-4381-1a63-fba3-0eb816fa5e61@amd.com> (raw)
In-Reply-To: <1511807458-27102-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org>
On 27/11/17 01:30 PM, Shaoyun Liu wrote:
> Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c
> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
> ---
> .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 ++++++++++++++++++++
> 1 file changed, 1248 insertions(+)
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
> new file mode 100644
> index 0000000..76cb748
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
> @@ -0,0 +1,1248 @@
> +#ifndef _ip_offset_1_HEADER
> +#define _ip_offset_1_HEADER
> +
> +#define MAX_INSTANCE 5
> +#define MAX_SEGMENT 5
> +
> +
> +struct IP_BASE_INSTANCE
> +{
> + unsigned int segment[MAX_SEGMENT];
> +};
> +
> +struct IP_BASE
> +{
> + struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
> +};
> +
> +
> +static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
> +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
> +static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers
> +static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } },
> + { { 0x00016E00, 0, 0, 0, 0 } },
> + { { 0x00017000, 0, 0, 0, 0 } },
> + { { 0x00017200, 0, 0, 0, 0 } },
> + { { 0x00017E00, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
Since these are likely to be ASIC specific wouldn't it make more sense
to organize these as one global struct/array per asic instead?
Variables like FUSE_BASE don't take into account that future ASICs might
also have a FUSE IP block but with different offsets.
> +
> +
> +#define NBIF_BASE__INST0_SEG0 0x00000000
> +#define NBIF_BASE__INST0_SEG1 0x00000014
> +#define NBIF_BASE__INST0_SEG2 0x00000D20
> +#define NBIF_BASE__INST0_SEG3 0x00010400
> +#define NBIF_BASE__INST0_SEG4 0
If we have the arrays above why keep these? At the very least the two
should be intertwined so changing one changes the other (if we don't
drop the define blocks).
Tom
> +
> +#define NBIF_BASE__INST1_SEG0 0
> +#define NBIF_BASE__INST1_SEG1 0
> +#define NBIF_BASE__INST1_SEG2 0
> +#define NBIF_BASE__INST1_SEG3 0
> +#define NBIF_BASE__INST1_SEG4 0
> +
> +#define NBIF_BASE__INST2_SEG0 0
> +#define NBIF_BASE__INST2_SEG1 0
> +#define NBIF_BASE__INST2_SEG2 0
> +#define NBIF_BASE__INST2_SEG3 0
> +#define NBIF_BASE__INST2_SEG4 0
> +
> +#define NBIF_BASE__INST3_SEG0 0
> +#define NBIF_BASE__INST3_SEG1 0
> +#define NBIF_BASE__INST3_SEG2 0
> +#define NBIF_BASE__INST3_SEG3 0
> +#define NBIF_BASE__INST3_SEG4 0
> +
> +#define NBIF_BASE__INST4_SEG0 0
> +#define NBIF_BASE__INST4_SEG1 0
> +#define NBIF_BASE__INST4_SEG2 0
> +#define NBIF_BASE__INST4_SEG3 0
> +#define NBIF_BASE__INST4_SEG4 0
> +
> +#define NBIO_BASE__INST0_SEG0 0x00000000
> +#define NBIO_BASE__INST0_SEG1 0x00000014
> +#define NBIO_BASE__INST0_SEG2 0x00000D20
> +#define NBIO_BASE__INST0_SEG3 0x00010400
> +#define NBIO_BASE__INST0_SEG4 0
> +
> +#define NBIO_BASE__INST1_SEG0 0
> +#define NBIO_BASE__INST1_SEG1 0
> +#define NBIO_BASE__INST1_SEG2 0
> +#define NBIO_BASE__INST1_SEG3 0
> +#define NBIO_BASE__INST1_SEG4 0
> +
> +#define NBIO_BASE__INST2_SEG0 0
> +#define NBIO_BASE__INST2_SEG1 0
> +#define NBIO_BASE__INST2_SEG2 0
> +#define NBIO_BASE__INST2_SEG3 0
> +#define NBIO_BASE__INST2_SEG4 0
> +
> +#define NBIO_BASE__INST3_SEG0 0
> +#define NBIO_BASE__INST3_SEG1 0
> +#define NBIO_BASE__INST3_SEG2 0
> +#define NBIO_BASE__INST3_SEG3 0
> +#define NBIO_BASE__INST3_SEG4 0
> +
> +#define NBIO_BASE__INST4_SEG0 0
> +#define NBIO_BASE__INST4_SEG1 0
> +#define NBIO_BASE__INST4_SEG2 0
> +#define NBIO_BASE__INST4_SEG3 0
> +#define NBIO_BASE__INST4_SEG4 0
> +
> +#define DCE_BASE__INST0_SEG0 0x00000012
> +#define DCE_BASE__INST0_SEG1 0x000000C0
> +#define DCE_BASE__INST0_SEG2 0x000034C0
> +#define DCE_BASE__INST0_SEG3 0
> +#define DCE_BASE__INST0_SEG4 0
> +
> +#define DCE_BASE__INST1_SEG0 0
> +#define DCE_BASE__INST1_SEG1 0
> +#define DCE_BASE__INST1_SEG2 0
> +#define DCE_BASE__INST1_SEG3 0
> +#define DCE_BASE__INST1_SEG4 0
> +
> +#define DCE_BASE__INST2_SEG0 0
> +#define DCE_BASE__INST2_SEG1 0
> +#define DCE_BASE__INST2_SEG2 0
> +#define DCE_BASE__INST2_SEG3 0
> +#define DCE_BASE__INST2_SEG4 0
> +
> +#define DCE_BASE__INST3_SEG0 0
> +#define DCE_BASE__INST3_SEG1 0
> +#define DCE_BASE__INST3_SEG2 0
> +#define DCE_BASE__INST3_SEG3 0
> +#define DCE_BASE__INST3_SEG4 0
> +
> +#define DCE_BASE__INST4_SEG0 0
> +#define DCE_BASE__INST4_SEG1 0
> +#define DCE_BASE__INST4_SEG2 0
> +#define DCE_BASE__INST4_SEG3 0
> +#define DCE_BASE__INST4_SEG4 0
> +
> +#define DCN_BASE__INST0_SEG0 0x00000012
> +#define DCN_BASE__INST0_SEG1 0x000000C0
> +#define DCN_BASE__INST0_SEG2 0x000034C0
> +#define DCN_BASE__INST0_SEG3 0
> +#define DCN_BASE__INST0_SEG4 0
> +
> +#define DCN_BASE__INST1_SEG0 0
> +#define DCN_BASE__INST1_SEG1 0
> +#define DCN_BASE__INST1_SEG2 0
> +#define DCN_BASE__INST1_SEG3 0
> +#define DCN_BASE__INST1_SEG4 0
> +
> +#define DCN_BASE__INST2_SEG0 0
> +#define DCN_BASE__INST2_SEG1 0
> +#define DCN_BASE__INST2_SEG2 0
> +#define DCN_BASE__INST2_SEG3 0
> +#define DCN_BASE__INST2_SEG4 0
> +
> +#define DCN_BASE__INST3_SEG0 0
> +#define DCN_BASE__INST3_SEG1 0
> +#define DCN_BASE__INST3_SEG2 0
> +#define DCN_BASE__INST3_SEG3 0
> +#define DCN_BASE__INST3_SEG4 0
> +
> +#define DCN_BASE__INST4_SEG0 0
> +#define DCN_BASE__INST4_SEG1 0
> +#define DCN_BASE__INST4_SEG2 0
> +#define DCN_BASE__INST4_SEG3 0
> +#define DCN_BASE__INST4_SEG4 0
> +
> +#define MP0_BASE__INST0_SEG0 0x00016000
> +#define MP0_BASE__INST0_SEG1 0
> +#define MP0_BASE__INST0_SEG2 0
> +#define MP0_BASE__INST0_SEG3 0
> +#define MP0_BASE__INST0_SEG4 0
> +
> +#define MP0_BASE__INST1_SEG0 0
> +#define MP0_BASE__INST1_SEG1 0
> +#define MP0_BASE__INST1_SEG2 0
> +#define MP0_BASE__INST1_SEG3 0
> +#define MP0_BASE__INST1_SEG4 0
> +
> +#define MP0_BASE__INST2_SEG0 0
> +#define MP0_BASE__INST2_SEG1 0
> +#define MP0_BASE__INST2_SEG2 0
> +#define MP0_BASE__INST2_SEG3 0
> +#define MP0_BASE__INST2_SEG4 0
> +
> +#define MP0_BASE__INST3_SEG0 0
> +#define MP0_BASE__INST3_SEG1 0
> +#define MP0_BASE__INST3_SEG2 0
> +#define MP0_BASE__INST3_SEG3 0
> +#define MP0_BASE__INST3_SEG4 0
> +
> +#define MP0_BASE__INST4_SEG0 0
> +#define MP0_BASE__INST4_SEG1 0
> +#define MP0_BASE__INST4_SEG2 0
> +#define MP0_BASE__INST4_SEG3 0
> +#define MP0_BASE__INST4_SEG4 0
> +
> +#define MP1_BASE__INST0_SEG0 0x00016000
> +#define MP1_BASE__INST0_SEG1 0
> +#define MP1_BASE__INST0_SEG2 0
> +#define MP1_BASE__INST0_SEG3 0
> +#define MP1_BASE__INST0_SEG4 0
> +
> +#define MP1_BASE__INST1_SEG0 0
> +#define MP1_BASE__INST1_SEG1 0
> +#define MP1_BASE__INST1_SEG2 0
> +#define MP1_BASE__INST1_SEG3 0
> +#define MP1_BASE__INST1_SEG4 0
> +
> +#define MP1_BASE__INST2_SEG0 0
> +#define MP1_BASE__INST2_SEG1 0
> +#define MP1_BASE__INST2_SEG2 0
> +#define MP1_BASE__INST2_SEG3 0
> +#define MP1_BASE__INST2_SEG4 0
> +
> +#define MP1_BASE__INST3_SEG0 0
> +#define MP1_BASE__INST3_SEG1 0
> +#define MP1_BASE__INST3_SEG2 0
> +#define MP1_BASE__INST3_SEG3 0
> +#define MP1_BASE__INST3_SEG4 0
> +
> +#define MP1_BASE__INST4_SEG0 0
> +#define MP1_BASE__INST4_SEG1 0
> +#define MP1_BASE__INST4_SEG2 0
> +#define MP1_BASE__INST4_SEG3 0
> +#define MP1_BASE__INST4_SEG4 0
> +
> +#define MP2_BASE__INST0_SEG0 0x00016000
> +#define MP2_BASE__INST0_SEG1 0
> +#define MP2_BASE__INST0_SEG2 0
> +#define MP2_BASE__INST0_SEG3 0
> +#define MP2_BASE__INST0_SEG4 0
> +
> +#define MP2_BASE__INST1_SEG0 0
> +#define MP2_BASE__INST1_SEG1 0
> +#define MP2_BASE__INST1_SEG2 0
> +#define MP2_BASE__INST1_SEG3 0
> +#define MP2_BASE__INST1_SEG4 0
> +
> +#define MP2_BASE__INST2_SEG0 0
> +#define MP2_BASE__INST2_SEG1 0
> +#define MP2_BASE__INST2_SEG2 0
> +#define MP2_BASE__INST2_SEG3 0
> +#define MP2_BASE__INST2_SEG4 0
> +
> +#define MP2_BASE__INST3_SEG0 0
> +#define MP2_BASE__INST3_SEG1 0
> +#define MP2_BASE__INST3_SEG2 0
> +#define MP2_BASE__INST3_SEG3 0
> +#define MP2_BASE__INST3_SEG4 0
> +
> +#define MP2_BASE__INST4_SEG0 0
> +#define MP2_BASE__INST4_SEG1 0
> +#define MP2_BASE__INST4_SEG2 0
> +#define MP2_BASE__INST4_SEG3 0
> +#define MP2_BASE__INST4_SEG4 0
> +
> +#define DF_BASE__INST0_SEG0 0x00007000
> +#define DF_BASE__INST0_SEG1 0
> +#define DF_BASE__INST0_SEG2 0
> +#define DF_BASE__INST0_SEG3 0
> +#define DF_BASE__INST0_SEG4 0
> +
> +#define DF_BASE__INST1_SEG0 0
> +#define DF_BASE__INST1_SEG1 0
> +#define DF_BASE__INST1_SEG2 0
> +#define DF_BASE__INST1_SEG3 0
> +#define DF_BASE__INST1_SEG4 0
> +
> +#define DF_BASE__INST2_SEG0 0
> +#define DF_BASE__INST2_SEG1 0
> +#define DF_BASE__INST2_SEG2 0
> +#define DF_BASE__INST2_SEG3 0
> +#define DF_BASE__INST2_SEG4 0
> +
> +#define DF_BASE__INST3_SEG0 0
> +#define DF_BASE__INST3_SEG1 0
> +#define DF_BASE__INST3_SEG2 0
> +#define DF_BASE__INST3_SEG3 0
> +#define DF_BASE__INST3_SEG4 0
> +
> +#define DF_BASE__INST4_SEG0 0
> +#define DF_BASE__INST4_SEG1 0
> +#define DF_BASE__INST4_SEG2 0
> +#define DF_BASE__INST4_SEG3 0
> +#define DF_BASE__INST4_SEG4 0
> +
> +#define UVD_BASE__INST0_SEG0 0x00007800
> +#define UVD_BASE__INST0_SEG1 0x00007E00
> +#define UVD_BASE__INST0_SEG2 0
> +#define UVD_BASE__INST0_SEG3 0
> +#define UVD_BASE__INST0_SEG4 0
> +
> +#define UVD_BASE__INST1_SEG0 0
> +#define UVD_BASE__INST1_SEG1 0
> +#define UVD_BASE__INST1_SEG2 0
> +#define UVD_BASE__INST1_SEG3 0
> +#define UVD_BASE__INST1_SEG4 0
> +
> +#define UVD_BASE__INST2_SEG0 0
> +#define UVD_BASE__INST2_SEG1 0
> +#define UVD_BASE__INST2_SEG2 0
> +#define UVD_BASE__INST2_SEG3 0
> +#define UVD_BASE__INST2_SEG4 0
> +
> +#define UVD_BASE__INST3_SEG0 0
> +#define UVD_BASE__INST3_SEG1 0
> +#define UVD_BASE__INST3_SEG2 0
> +#define UVD_BASE__INST3_SEG3 0
> +#define UVD_BASE__INST3_SEG4 0
> +
> +#define UVD_BASE__INST4_SEG0 0
> +#define UVD_BASE__INST4_SEG1 0
> +#define UVD_BASE__INST4_SEG2 0
> +#define UVD_BASE__INST4_SEG3 0
> +#define UVD_BASE__INST4_SEG4 0
> +
> +#define VCN_BASE__INST0_SEG0 0x00007800
> +#define VCN_BASE__INST0_SEG1 0x00007E00
> +#define VCN_BASE__INST0_SEG2 0
> +#define VCN_BASE__INST0_SEG3 0
> +#define VCN_BASE__INST0_SEG4 0
> +
> +#define VCN_BASE__INST1_SEG0 0
> +#define VCN_BASE__INST1_SEG1 0
> +#define VCN_BASE__INST1_SEG2 0
> +#define VCN_BASE__INST1_SEG3 0
> +#define VCN_BASE__INST1_SEG4 0
> +
> +#define VCN_BASE__INST2_SEG0 0
> +#define VCN_BASE__INST2_SEG1 0
> +#define VCN_BASE__INST2_SEG2 0
> +#define VCN_BASE__INST2_SEG3 0
> +#define VCN_BASE__INST2_SEG4 0
> +
> +#define VCN_BASE__INST3_SEG0 0
> +#define VCN_BASE__INST3_SEG1 0
> +#define VCN_BASE__INST3_SEG2 0
> +#define VCN_BASE__INST3_SEG3 0
> +#define VCN_BASE__INST3_SEG4 0
> +
> +#define VCN_BASE__INST4_SEG0 0
> +#define VCN_BASE__INST4_SEG1 0
> +#define VCN_BASE__INST4_SEG2 0
> +#define VCN_BASE__INST4_SEG3 0
> +#define VCN_BASE__INST4_SEG4 0
> +
> +#define DBGU_BASE__INST0_SEG0 0x00000180
> +#define DBGU_BASE__INST0_SEG1 0x000001A0
> +#define DBGU_BASE__INST0_SEG2 0
> +#define DBGU_BASE__INST0_SEG3 0
> +#define DBGU_BASE__INST0_SEG4 0
> +
> +#define DBGU_BASE__INST1_SEG0 0
> +#define DBGU_BASE__INST1_SEG1 0
> +#define DBGU_BASE__INST1_SEG2 0
> +#define DBGU_BASE__INST1_SEG3 0
> +#define DBGU_BASE__INST1_SEG4 0
> +
> +#define DBGU_BASE__INST2_SEG0 0
> +#define DBGU_BASE__INST2_SEG1 0
> +#define DBGU_BASE__INST2_SEG2 0
> +#define DBGU_BASE__INST2_SEG3 0
> +#define DBGU_BASE__INST2_SEG4 0
> +
> +#define DBGU_BASE__INST3_SEG0 0
> +#define DBGU_BASE__INST3_SEG1 0
> +#define DBGU_BASE__INST3_SEG2 0
> +#define DBGU_BASE__INST3_SEG3 0
> +#define DBGU_BASE__INST3_SEG4 0
> +
> +#define DBGU_BASE__INST4_SEG0 0
> +#define DBGU_BASE__INST4_SEG1 0
> +#define DBGU_BASE__INST4_SEG2 0
> +#define DBGU_BASE__INST4_SEG3 0
> +#define DBGU_BASE__INST4_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0
> +#define DBGU_NBIO_BASE__INST0_SEG1 0
> +#define DBGU_NBIO_BASE__INST0_SEG2 0
> +#define DBGU_NBIO_BASE__INST0_SEG3 0
> +#define DBGU_NBIO_BASE__INST0_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST1_SEG0 0
> +#define DBGU_NBIO_BASE__INST1_SEG1 0
> +#define DBGU_NBIO_BASE__INST1_SEG2 0
> +#define DBGU_NBIO_BASE__INST1_SEG3 0
> +#define DBGU_NBIO_BASE__INST1_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST2_SEG0 0
> +#define DBGU_NBIO_BASE__INST2_SEG1 0
> +#define DBGU_NBIO_BASE__INST2_SEG2 0
> +#define DBGU_NBIO_BASE__INST2_SEG3 0
> +#define DBGU_NBIO_BASE__INST2_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST3_SEG0 0
> +#define DBGU_NBIO_BASE__INST3_SEG1 0
> +#define DBGU_NBIO_BASE__INST3_SEG2 0
> +#define DBGU_NBIO_BASE__INST3_SEG3 0
> +#define DBGU_NBIO_BASE__INST3_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST4_SEG0 0
> +#define DBGU_NBIO_BASE__INST4_SEG1 0
> +#define DBGU_NBIO_BASE__INST4_SEG2 0
> +#define DBGU_NBIO_BASE__INST4_SEG3 0
> +#define DBGU_NBIO_BASE__INST4_SEG4 0
> +
> +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0
> +#define DBGU_IO_BASE__INST0_SEG1 0
> +#define DBGU_IO_BASE__INST0_SEG2 0
> +#define DBGU_IO_BASE__INST0_SEG3 0
> +#define DBGU_IO_BASE__INST0_SEG4 0
> +
> +#define DBGU_IO_BASE__INST1_SEG0 0
> +#define DBGU_IO_BASE__INST1_SEG1 0
> +#define DBGU_IO_BASE__INST1_SEG2 0
> +#define DBGU_IO_BASE__INST1_SEG3 0
> +#define DBGU_IO_BASE__INST1_SEG4 0
> +
> +#define DBGU_IO_BASE__INST2_SEG0 0
> +#define DBGU_IO_BASE__INST2_SEG1 0
> +#define DBGU_IO_BASE__INST2_SEG2 0
> +#define DBGU_IO_BASE__INST2_SEG3 0
> +#define DBGU_IO_BASE__INST2_SEG4 0
> +
> +#define DBGU_IO_BASE__INST3_SEG0 0
> +#define DBGU_IO_BASE__INST3_SEG1 0
> +#define DBGU_IO_BASE__INST3_SEG2 0
> +#define DBGU_IO_BASE__INST3_SEG3 0
> +#define DBGU_IO_BASE__INST3_SEG4 0
> +
> +#define DBGU_IO_BASE__INST4_SEG0 0
> +#define DBGU_IO_BASE__INST4_SEG1 0
> +#define DBGU_IO_BASE__INST4_SEG2 0
> +#define DBGU_IO_BASE__INST4_SEG3 0
> +#define DBGU_IO_BASE__INST4_SEG4 0
> +
> +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0
> +#define DFX_DAP_BASE__INST0_SEG1 0
> +#define DFX_DAP_BASE__INST0_SEG2 0
> +#define DFX_DAP_BASE__INST0_SEG3 0
> +#define DFX_DAP_BASE__INST0_SEG4 0
> +
> +#define DFX_DAP_BASE__INST1_SEG0 0
> +#define DFX_DAP_BASE__INST1_SEG1 0
> +#define DFX_DAP_BASE__INST1_SEG2 0
> +#define DFX_DAP_BASE__INST1_SEG3 0
> +#define DFX_DAP_BASE__INST1_SEG4 0
> +
> +#define DFX_DAP_BASE__INST2_SEG0 0
> +#define DFX_DAP_BASE__INST2_SEG1 0
> +#define DFX_DAP_BASE__INST2_SEG2 0
> +#define DFX_DAP_BASE__INST2_SEG3 0
> +#define DFX_DAP_BASE__INST2_SEG4 0
> +
> +#define DFX_DAP_BASE__INST3_SEG0 0
> +#define DFX_DAP_BASE__INST3_SEG1 0
> +#define DFX_DAP_BASE__INST3_SEG2 0
> +#define DFX_DAP_BASE__INST3_SEG3 0
> +#define DFX_DAP_BASE__INST3_SEG4 0
> +
> +#define DFX_DAP_BASE__INST4_SEG0 0
> +#define DFX_DAP_BASE__INST4_SEG1 0
> +#define DFX_DAP_BASE__INST4_SEG2 0
> +#define DFX_DAP_BASE__INST4_SEG3 0
> +#define DFX_DAP_BASE__INST4_SEG4 0
> +
> +#define DFX_BASE__INST0_SEG0 0x00000580
> +#define DFX_BASE__INST0_SEG1 0
> +#define DFX_BASE__INST0_SEG2 0
> +#define DFX_BASE__INST0_SEG3 0
> +#define DFX_BASE__INST0_SEG4 0
> +
> +#define DFX_BASE__INST1_SEG0 0
> +#define DFX_BASE__INST1_SEG1 0
> +#define DFX_BASE__INST1_SEG2 0
> +#define DFX_BASE__INST1_SEG3 0
> +#define DFX_BASE__INST1_SEG4 0
> +
> +#define DFX_BASE__INST2_SEG0 0
> +#define DFX_BASE__INST2_SEG1 0
> +#define DFX_BASE__INST2_SEG2 0
> +#define DFX_BASE__INST2_SEG3 0
> +#define DFX_BASE__INST2_SEG4 0
> +
> +#define DFX_BASE__INST3_SEG0 0
> +#define DFX_BASE__INST3_SEG1 0
> +#define DFX_BASE__INST3_SEG2 0
> +#define DFX_BASE__INST3_SEG3 0
> +#define DFX_BASE__INST3_SEG4 0
> +
> +#define DFX_BASE__INST4_SEG0 0
> +#define DFX_BASE__INST4_SEG1 0
> +#define DFX_BASE__INST4_SEG2 0
> +#define DFX_BASE__INST4_SEG3 0
> +#define DFX_BASE__INST4_SEG4 0
> +
> +#define ISP_BASE__INST0_SEG0 0x00018000
> +#define ISP_BASE__INST0_SEG1 0
> +#define ISP_BASE__INST0_SEG2 0
> +#define ISP_BASE__INST0_SEG3 0
> +#define ISP_BASE__INST0_SEG4 0
> +
> +#define ISP_BASE__INST1_SEG0 0
> +#define ISP_BASE__INST1_SEG1 0
> +#define ISP_BASE__INST1_SEG2 0
> +#define ISP_BASE__INST1_SEG3 0
> +#define ISP_BASE__INST1_SEG4 0
> +
> +#define ISP_BASE__INST2_SEG0 0
> +#define ISP_BASE__INST2_SEG1 0
> +#define ISP_BASE__INST2_SEG2 0
> +#define ISP_BASE__INST2_SEG3 0
> +#define ISP_BASE__INST2_SEG4 0
> +
> +#define ISP_BASE__INST3_SEG0 0
> +#define ISP_BASE__INST3_SEG1 0
> +#define ISP_BASE__INST3_SEG2 0
> +#define ISP_BASE__INST3_SEG3 0
> +#define ISP_BASE__INST3_SEG4 0
> +
> +#define ISP_BASE__INST4_SEG0 0
> +#define ISP_BASE__INST4_SEG1 0
> +#define ISP_BASE__INST4_SEG2 0
> +#define ISP_BASE__INST4_SEG3 0
> +#define ISP_BASE__INST4_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0
> +#define SYSTEMHUB_BASE__INST0_SEG1 0
> +#define SYSTEMHUB_BASE__INST0_SEG2 0
> +#define SYSTEMHUB_BASE__INST0_SEG3 0
> +#define SYSTEMHUB_BASE__INST0_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST1_SEG0 0
> +#define SYSTEMHUB_BASE__INST1_SEG1 0
> +#define SYSTEMHUB_BASE__INST1_SEG2 0
> +#define SYSTEMHUB_BASE__INST1_SEG3 0
> +#define SYSTEMHUB_BASE__INST1_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST2_SEG0 0
> +#define SYSTEMHUB_BASE__INST2_SEG1 0
> +#define SYSTEMHUB_BASE__INST2_SEG2 0
> +#define SYSTEMHUB_BASE__INST2_SEG3 0
> +#define SYSTEMHUB_BASE__INST2_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST3_SEG0 0
> +#define SYSTEMHUB_BASE__INST3_SEG1 0
> +#define SYSTEMHUB_BASE__INST3_SEG2 0
> +#define SYSTEMHUB_BASE__INST3_SEG3 0
> +#define SYSTEMHUB_BASE__INST3_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST4_SEG0 0
> +#define SYSTEMHUB_BASE__INST4_SEG1 0
> +#define SYSTEMHUB_BASE__INST4_SEG2 0
> +#define SYSTEMHUB_BASE__INST4_SEG3 0
> +#define SYSTEMHUB_BASE__INST4_SEG4 0
> +
> +#define L2IMU_BASE__INST0_SEG0 0x00007DC0
> +#define L2IMU_BASE__INST0_SEG1 0
> +#define L2IMU_BASE__INST0_SEG2 0
> +#define L2IMU_BASE__INST0_SEG3 0
> +#define L2IMU_BASE__INST0_SEG4 0
> +
> +#define L2IMU_BASE__INST1_SEG0 0
> +#define L2IMU_BASE__INST1_SEG1 0
> +#define L2IMU_BASE__INST1_SEG2 0
> +#define L2IMU_BASE__INST1_SEG3 0
> +#define L2IMU_BASE__INST1_SEG4 0
> +
> +#define L2IMU_BASE__INST2_SEG0 0
> +#define L2IMU_BASE__INST2_SEG1 0
> +#define L2IMU_BASE__INST2_SEG2 0
> +#define L2IMU_BASE__INST2_SEG3 0
> +#define L2IMU_BASE__INST2_SEG4 0
> +
> +#define L2IMU_BASE__INST3_SEG0 0
> +#define L2IMU_BASE__INST3_SEG1 0
> +#define L2IMU_BASE__INST3_SEG2 0
> +#define L2IMU_BASE__INST3_SEG3 0
> +#define L2IMU_BASE__INST3_SEG4 0
> +
> +#define L2IMU_BASE__INST4_SEG0 0
> +#define L2IMU_BASE__INST4_SEG1 0
> +#define L2IMU_BASE__INST4_SEG2 0
> +#define L2IMU_BASE__INST4_SEG3 0
> +#define L2IMU_BASE__INST4_SEG4 0
> +
> +#define IOHC_BASE__INST0_SEG0 0x00010000
> +#define IOHC_BASE__INST0_SEG1 0
> +#define IOHC_BASE__INST0_SEG2 0
> +#define IOHC_BASE__INST0_SEG3 0
> +#define IOHC_BASE__INST0_SEG4 0
> +
> +#define IOHC_BASE__INST1_SEG0 0
> +#define IOHC_BASE__INST1_SEG1 0
> +#define IOHC_BASE__INST1_SEG2 0
> +#define IOHC_BASE__INST1_SEG3 0
> +#define IOHC_BASE__INST1_SEG4 0
> +
> +#define IOHC_BASE__INST2_SEG0 0
> +#define IOHC_BASE__INST2_SEG1 0
> +#define IOHC_BASE__INST2_SEG2 0
> +#define IOHC_BASE__INST2_SEG3 0
> +#define IOHC_BASE__INST2_SEG4 0
> +
> +#define IOHC_BASE__INST3_SEG0 0
> +#define IOHC_BASE__INST3_SEG1 0
> +#define IOHC_BASE__INST3_SEG2 0
> +#define IOHC_BASE__INST3_SEG3 0
> +#define IOHC_BASE__INST3_SEG4 0
> +
> +#define IOHC_BASE__INST4_SEG0 0
> +#define IOHC_BASE__INST4_SEG1 0
> +#define IOHC_BASE__INST4_SEG2 0
> +#define IOHC_BASE__INST4_SEG3 0
> +#define IOHC_BASE__INST4_SEG4 0
> +
> +#define ATHUB_BASE__INST0_SEG0 0x00000C20
> +#define ATHUB_BASE__INST0_SEG1 0
> +#define ATHUB_BASE__INST0_SEG2 0
> +#define ATHUB_BASE__INST0_SEG3 0
> +#define ATHUB_BASE__INST0_SEG4 0
> +
> +#define ATHUB_BASE__INST1_SEG0 0
> +#define ATHUB_BASE__INST1_SEG1 0
> +#define ATHUB_BASE__INST1_SEG2 0
> +#define ATHUB_BASE__INST1_SEG3 0
> +#define ATHUB_BASE__INST1_SEG4 0
> +
> +#define ATHUB_BASE__INST2_SEG0 0
> +#define ATHUB_BASE__INST2_SEG1 0
> +#define ATHUB_BASE__INST2_SEG2 0
> +#define ATHUB_BASE__INST2_SEG3 0
> +#define ATHUB_BASE__INST2_SEG4 0
> +
> +#define ATHUB_BASE__INST3_SEG0 0
> +#define ATHUB_BASE__INST3_SEG1 0
> +#define ATHUB_BASE__INST3_SEG2 0
> +#define ATHUB_BASE__INST3_SEG3 0
> +#define ATHUB_BASE__INST3_SEG4 0
> +
> +#define ATHUB_BASE__INST4_SEG0 0
> +#define ATHUB_BASE__INST4_SEG1 0
> +#define ATHUB_BASE__INST4_SEG2 0
> +#define ATHUB_BASE__INST4_SEG3 0
> +#define ATHUB_BASE__INST4_SEG4 0
> +
> +#define VCE_BASE__INST0_SEG0 0x00007E00
> +#define VCE_BASE__INST0_SEG1 0x00048800
> +#define VCE_BASE__INST0_SEG2 0
> +#define VCE_BASE__INST0_SEG3 0
> +#define VCE_BASE__INST0_SEG4 0
> +
> +#define VCE_BASE__INST1_SEG0 0
> +#define VCE_BASE__INST1_SEG1 0
> +#define VCE_BASE__INST1_SEG2 0
> +#define VCE_BASE__INST1_SEG3 0
> +#define VCE_BASE__INST1_SEG4 0
> +
> +#define VCE_BASE__INST2_SEG0 0
> +#define VCE_BASE__INST2_SEG1 0
> +#define VCE_BASE__INST2_SEG2 0
> +#define VCE_BASE__INST2_SEG3 0
> +#define VCE_BASE__INST2_SEG4 0
> +
> +#define VCE_BASE__INST3_SEG0 0
> +#define VCE_BASE__INST3_SEG1 0
> +#define VCE_BASE__INST3_SEG2 0
> +#define VCE_BASE__INST3_SEG3 0
> +#define VCE_BASE__INST3_SEG4 0
> +
> +#define VCE_BASE__INST4_SEG0 0
> +#define VCE_BASE__INST4_SEG1 0
> +#define VCE_BASE__INST4_SEG2 0
> +#define VCE_BASE__INST4_SEG3 0
> +#define VCE_BASE__INST4_SEG4 0
> +
> +#define GC_BASE__INST0_SEG0 0x00002000
> +#define GC_BASE__INST0_SEG1 0x0000A000
> +#define GC_BASE__INST0_SEG2 0
> +#define GC_BASE__INST0_SEG3 0
> +#define GC_BASE__INST0_SEG4 0
> +
> +#define GC_BASE__INST1_SEG0 0
> +#define GC_BASE__INST1_SEG1 0
> +#define GC_BASE__INST1_SEG2 0
> +#define GC_BASE__INST1_SEG3 0
> +#define GC_BASE__INST1_SEG4 0
> +
> +#define GC_BASE__INST2_SEG0 0
> +#define GC_BASE__INST2_SEG1 0
> +#define GC_BASE__INST2_SEG2 0
> +#define GC_BASE__INST2_SEG3 0
> +#define GC_BASE__INST2_SEG4 0
> +
> +#define GC_BASE__INST3_SEG0 0
> +#define GC_BASE__INST3_SEG1 0
> +#define GC_BASE__INST3_SEG2 0
> +#define GC_BASE__INST3_SEG3 0
> +#define GC_BASE__INST3_SEG4 0
> +
> +#define GC_BASE__INST4_SEG0 0
> +#define GC_BASE__INST4_SEG1 0
> +#define GC_BASE__INST4_SEG2 0
> +#define GC_BASE__INST4_SEG3 0
> +#define GC_BASE__INST4_SEG4 0
> +
> +#define MMHUB_BASE__INST0_SEG0 0x0001A000
> +#define MMHUB_BASE__INST0_SEG1 0
> +#define MMHUB_BASE__INST0_SEG2 0
> +#define MMHUB_BASE__INST0_SEG3 0
> +#define MMHUB_BASE__INST0_SEG4 0
> +
> +#define MMHUB_BASE__INST1_SEG0 0
> +#define MMHUB_BASE__INST1_SEG1 0
> +#define MMHUB_BASE__INST1_SEG2 0
> +#define MMHUB_BASE__INST1_SEG3 0
> +#define MMHUB_BASE__INST1_SEG4 0
> +
> +#define MMHUB_BASE__INST2_SEG0 0
> +#define MMHUB_BASE__INST2_SEG1 0
> +#define MMHUB_BASE__INST2_SEG2 0
> +#define MMHUB_BASE__INST2_SEG3 0
> +#define MMHUB_BASE__INST2_SEG4 0
> +
> +#define MMHUB_BASE__INST3_SEG0 0
> +#define MMHUB_BASE__INST3_SEG1 0
> +#define MMHUB_BASE__INST3_SEG2 0
> +#define MMHUB_BASE__INST3_SEG3 0
> +#define MMHUB_BASE__INST3_SEG4 0
> +
> +#define MMHUB_BASE__INST4_SEG0 0
> +#define MMHUB_BASE__INST4_SEG1 0
> +#define MMHUB_BASE__INST4_SEG2 0
> +#define MMHUB_BASE__INST4_SEG3 0
> +#define MMHUB_BASE__INST4_SEG4 0
> +
> +#define RSMU_BASE__INST0_SEG0 0x00012000
> +#define RSMU_BASE__INST0_SEG1 0
> +#define RSMU_BASE__INST0_SEG2 0
> +#define RSMU_BASE__INST0_SEG3 0
> +#define RSMU_BASE__INST0_SEG4 0
> +
> +#define RSMU_BASE__INST1_SEG0 0
> +#define RSMU_BASE__INST1_SEG1 0
> +#define RSMU_BASE__INST1_SEG2 0
> +#define RSMU_BASE__INST1_SEG3 0
> +#define RSMU_BASE__INST1_SEG4 0
> +
> +#define RSMU_BASE__INST2_SEG0 0
> +#define RSMU_BASE__INST2_SEG1 0
> +#define RSMU_BASE__INST2_SEG2 0
> +#define RSMU_BASE__INST2_SEG3 0
> +#define RSMU_BASE__INST2_SEG4 0
> +
> +#define RSMU_BASE__INST3_SEG0 0
> +#define RSMU_BASE__INST3_SEG1 0
> +#define RSMU_BASE__INST3_SEG2 0
> +#define RSMU_BASE__INST3_SEG3 0
> +#define RSMU_BASE__INST3_SEG4 0
> +
> +#define RSMU_BASE__INST4_SEG0 0
> +#define RSMU_BASE__INST4_SEG1 0
> +#define RSMU_BASE__INST4_SEG2 0
> +#define RSMU_BASE__INST4_SEG3 0
> +#define RSMU_BASE__INST4_SEG4 0
> +
> +#define HDP_BASE__INST0_SEG0 0x00000F20
> +#define HDP_BASE__INST0_SEG1 0
> +#define HDP_BASE__INST0_SEG2 0
> +#define HDP_BASE__INST0_SEG3 0
> +#define HDP_BASE__INST0_SEG4 0
> +
> +#define HDP_BASE__INST1_SEG0 0
> +#define HDP_BASE__INST1_SEG1 0
> +#define HDP_BASE__INST1_SEG2 0
> +#define HDP_BASE__INST1_SEG3 0
> +#define HDP_BASE__INST1_SEG4 0
> +
> +#define HDP_BASE__INST2_SEG0 0
> +#define HDP_BASE__INST2_SEG1 0
> +#define HDP_BASE__INST2_SEG2 0
> +#define HDP_BASE__INST2_SEG3 0
> +#define HDP_BASE__INST2_SEG4 0
> +
> +#define HDP_BASE__INST3_SEG0 0
> +#define HDP_BASE__INST3_SEG1 0
> +#define HDP_BASE__INST3_SEG2 0
> +#define HDP_BASE__INST3_SEG3 0
> +#define HDP_BASE__INST3_SEG4 0
> +
> +#define HDP_BASE__INST4_SEG0 0
> +#define HDP_BASE__INST4_SEG1 0
> +#define HDP_BASE__INST4_SEG2 0
> +#define HDP_BASE__INST4_SEG3 0
> +#define HDP_BASE__INST4_SEG4 0
> +
> +#define OSSSYS_BASE__INST0_SEG0 0x000010A0
> +#define OSSSYS_BASE__INST0_SEG1 0
> +#define OSSSYS_BASE__INST0_SEG2 0
> +#define OSSSYS_BASE__INST0_SEG3 0
> +#define OSSSYS_BASE__INST0_SEG4 0
> +
> +#define OSSSYS_BASE__INST1_SEG0 0
> +#define OSSSYS_BASE__INST1_SEG1 0
> +#define OSSSYS_BASE__INST1_SEG2 0
> +#define OSSSYS_BASE__INST1_SEG3 0
> +#define OSSSYS_BASE__INST1_SEG4 0
> +
> +#define OSSSYS_BASE__INST2_SEG0 0
> +#define OSSSYS_BASE__INST2_SEG1 0
> +#define OSSSYS_BASE__INST2_SEG2 0
> +#define OSSSYS_BASE__INST2_SEG3 0
> +#define OSSSYS_BASE__INST2_SEG4 0
> +
> +#define OSSSYS_BASE__INST3_SEG0 0
> +#define OSSSYS_BASE__INST3_SEG1 0
> +#define OSSSYS_BASE__INST3_SEG2 0
> +#define OSSSYS_BASE__INST3_SEG3 0
> +#define OSSSYS_BASE__INST3_SEG4 0
> +
> +#define OSSSYS_BASE__INST4_SEG0 0
> +#define OSSSYS_BASE__INST4_SEG1 0
> +#define OSSSYS_BASE__INST4_SEG2 0
> +#define OSSSYS_BASE__INST4_SEG3 0
> +#define OSSSYS_BASE__INST4_SEG4 0
> +
> +#define SDMA0_BASE__INST0_SEG0 0x00001260
> +#define SDMA0_BASE__INST0_SEG1 0
> +#define SDMA0_BASE__INST0_SEG2 0
> +#define SDMA0_BASE__INST0_SEG3 0
> +#define SDMA0_BASE__INST0_SEG4 0
> +
> +#define SDMA0_BASE__INST1_SEG0 0
> +#define SDMA0_BASE__INST1_SEG1 0
> +#define SDMA0_BASE__INST1_SEG2 0
> +#define SDMA0_BASE__INST1_SEG3 0
> +#define SDMA0_BASE__INST1_SEG4 0
> +
> +#define SDMA0_BASE__INST2_SEG0 0
> +#define SDMA0_BASE__INST2_SEG1 0
> +#define SDMA0_BASE__INST2_SEG2 0
> +#define SDMA0_BASE__INST2_SEG3 0
> +#define SDMA0_BASE__INST2_SEG4 0
> +
> +#define SDMA0_BASE__INST3_SEG0 0
> +#define SDMA0_BASE__INST3_SEG1 0
> +#define SDMA0_BASE__INST3_SEG2 0
> +#define SDMA0_BASE__INST3_SEG3 0
> +#define SDMA0_BASE__INST3_SEG4 0
> +
> +#define SDMA0_BASE__INST4_SEG0 0
> +#define SDMA0_BASE__INST4_SEG1 0
> +#define SDMA0_BASE__INST4_SEG2 0
> +#define SDMA0_BASE__INST4_SEG3 0
> +#define SDMA0_BASE__INST4_SEG4 0
> +
> +#define SDMA1_BASE__INST0_SEG0 0x00001460
> +#define SDMA1_BASE__INST0_SEG1 0
> +#define SDMA1_BASE__INST0_SEG2 0
> +#define SDMA1_BASE__INST0_SEG3 0
> +#define SDMA1_BASE__INST0_SEG4 0
> +
> +#define SDMA1_BASE__INST1_SEG0 0
> +#define SDMA1_BASE__INST1_SEG1 0
> +#define SDMA1_BASE__INST1_SEG2 0
> +#define SDMA1_BASE__INST1_SEG3 0
> +#define SDMA1_BASE__INST1_SEG4 0
> +
> +#define SDMA1_BASE__INST2_SEG0 0
> +#define SDMA1_BASE__INST2_SEG1 0
> +#define SDMA1_BASE__INST2_SEG2 0
> +#define SDMA1_BASE__INST2_SEG3 0
> +#define SDMA1_BASE__INST2_SEG4 0
> +
> +#define SDMA1_BASE__INST3_SEG0 0
> +#define SDMA1_BASE__INST3_SEG1 0
> +#define SDMA1_BASE__INST3_SEG2 0
> +#define SDMA1_BASE__INST3_SEG3 0
> +#define SDMA1_BASE__INST3_SEG4 0
> +
> +#define SDMA1_BASE__INST4_SEG0 0
> +#define SDMA1_BASE__INST4_SEG1 0
> +#define SDMA1_BASE__INST4_SEG2 0
> +#define SDMA1_BASE__INST4_SEG3 0
> +#define SDMA1_BASE__INST4_SEG4 0
> +
> +#define XDMA_BASE__INST0_SEG0 0x00003400
> +#define XDMA_BASE__INST0_SEG1 0
> +#define XDMA_BASE__INST0_SEG2 0
> +#define XDMA_BASE__INST0_SEG3 0
> +#define XDMA_BASE__INST0_SEG4 0
> +
> +#define XDMA_BASE__INST1_SEG0 0
> +#define XDMA_BASE__INST1_SEG1 0
> +#define XDMA_BASE__INST1_SEG2 0
> +#define XDMA_BASE__INST1_SEG3 0
> +#define XDMA_BASE__INST1_SEG4 0
> +
> +#define XDMA_BASE__INST2_SEG0 0
> +#define XDMA_BASE__INST2_SEG1 0
> +#define XDMA_BASE__INST2_SEG2 0
> +#define XDMA_BASE__INST2_SEG3 0
> +#define XDMA_BASE__INST2_SEG4 0
> +
> +#define XDMA_BASE__INST3_SEG0 0
> +#define XDMA_BASE__INST3_SEG1 0
> +#define XDMA_BASE__INST3_SEG2 0
> +#define XDMA_BASE__INST3_SEG3 0
> +#define XDMA_BASE__INST3_SEG4 0
> +
> +#define XDMA_BASE__INST4_SEG0 0
> +#define XDMA_BASE__INST4_SEG1 0
> +#define XDMA_BASE__INST4_SEG2 0
> +#define XDMA_BASE__INST4_SEG3 0
> +#define XDMA_BASE__INST4_SEG4 0
> +
> +#define UMC_BASE__INST0_SEG0 0x00014000
> +#define UMC_BASE__INST0_SEG1 0
> +#define UMC_BASE__INST0_SEG2 0
> +#define UMC_BASE__INST0_SEG3 0
> +#define UMC_BASE__INST0_SEG4 0
> +
> +#define UMC_BASE__INST1_SEG0 0
> +#define UMC_BASE__INST1_SEG1 0
> +#define UMC_BASE__INST1_SEG2 0
> +#define UMC_BASE__INST1_SEG3 0
> +#define UMC_BASE__INST1_SEG4 0
> +
> +#define UMC_BASE__INST2_SEG0 0
> +#define UMC_BASE__INST2_SEG1 0
> +#define UMC_BASE__INST2_SEG2 0
> +#define UMC_BASE__INST2_SEG3 0
> +#define UMC_BASE__INST2_SEG4 0
> +
> +#define UMC_BASE__INST3_SEG0 0
> +#define UMC_BASE__INST3_SEG1 0
> +#define UMC_BASE__INST3_SEG2 0
> +#define UMC_BASE__INST3_SEG3 0
> +#define UMC_BASE__INST3_SEG4 0
> +
> +#define UMC_BASE__INST4_SEG0 0
> +#define UMC_BASE__INST4_SEG1 0
> +#define UMC_BASE__INST4_SEG2 0
> +#define UMC_BASE__INST4_SEG3 0
> +#define UMC_BASE__INST4_SEG4 0
> +
> +#define THM_BASE__INST0_SEG0 0x00016600
> +#define THM_BASE__INST0_SEG1 0
> +#define THM_BASE__INST0_SEG2 0
> +#define THM_BASE__INST0_SEG3 0
> +#define THM_BASE__INST0_SEG4 0
> +
> +#define THM_BASE__INST1_SEG0 0
> +#define THM_BASE__INST1_SEG1 0
> +#define THM_BASE__INST1_SEG2 0
> +#define THM_BASE__INST1_SEG3 0
> +#define THM_BASE__INST1_SEG4 0
> +
> +#define THM_BASE__INST2_SEG0 0
> +#define THM_BASE__INST2_SEG1 0
> +#define THM_BASE__INST2_SEG2 0
> +#define THM_BASE__INST2_SEG3 0
> +#define THM_BASE__INST2_SEG4 0
> +
> +#define THM_BASE__INST3_SEG0 0
> +#define THM_BASE__INST3_SEG1 0
> +#define THM_BASE__INST3_SEG2 0
> +#define THM_BASE__INST3_SEG3 0
> +#define THM_BASE__INST3_SEG4 0
> +
> +#define THM_BASE__INST4_SEG0 0
> +#define THM_BASE__INST4_SEG1 0
> +#define THM_BASE__INST4_SEG2 0
> +#define THM_BASE__INST4_SEG3 0
> +#define THM_BASE__INST4_SEG4 0
> +
> +#define SMUIO_BASE__INST0_SEG0 0x00016800
> +#define SMUIO_BASE__INST0_SEG1 0
> +#define SMUIO_BASE__INST0_SEG2 0
> +#define SMUIO_BASE__INST0_SEG3 0
> +#define SMUIO_BASE__INST0_SEG4 0
> +
> +#define SMUIO_BASE__INST1_SEG0 0
> +#define SMUIO_BASE__INST1_SEG1 0
> +#define SMUIO_BASE__INST1_SEG2 0
> +#define SMUIO_BASE__INST1_SEG3 0
> +#define SMUIO_BASE__INST1_SEG4 0
> +
> +#define SMUIO_BASE__INST2_SEG0 0
> +#define SMUIO_BASE__INST2_SEG1 0
> +#define SMUIO_BASE__INST2_SEG2 0
> +#define SMUIO_BASE__INST2_SEG3 0
> +#define SMUIO_BASE__INST2_SEG4 0
> +
> +#define SMUIO_BASE__INST3_SEG0 0
> +#define SMUIO_BASE__INST3_SEG1 0
> +#define SMUIO_BASE__INST3_SEG2 0
> +#define SMUIO_BASE__INST3_SEG3 0
> +#define SMUIO_BASE__INST3_SEG4 0
> +
> +#define SMUIO_BASE__INST4_SEG0 0
> +#define SMUIO_BASE__INST4_SEG1 0
> +#define SMUIO_BASE__INST4_SEG2 0
> +#define SMUIO_BASE__INST4_SEG3 0
> +#define SMUIO_BASE__INST4_SEG4 0
> +
> +#define PWR_BASE__INST0_SEG0 0x00016A00
> +#define PWR_BASE__INST0_SEG1 0
> +#define PWR_BASE__INST0_SEG2 0
> +#define PWR_BASE__INST0_SEG3 0
> +#define PWR_BASE__INST0_SEG4 0
> +
> +#define PWR_BASE__INST1_SEG0 0
> +#define PWR_BASE__INST1_SEG1 0
> +#define PWR_BASE__INST1_SEG2 0
> +#define PWR_BASE__INST1_SEG3 0
> +#define PWR_BASE__INST1_SEG4 0
> +
> +#define PWR_BASE__INST2_SEG0 0
> +#define PWR_BASE__INST2_SEG1 0
> +#define PWR_BASE__INST2_SEG2 0
> +#define PWR_BASE__INST2_SEG3 0
> +#define PWR_BASE__INST2_SEG4 0
> +
> +#define PWR_BASE__INST3_SEG0 0
> +#define PWR_BASE__INST3_SEG1 0
> +#define PWR_BASE__INST3_SEG2 0
> +#define PWR_BASE__INST3_SEG3 0
> +#define PWR_BASE__INST3_SEG4 0
> +
> +#define PWR_BASE__INST4_SEG0 0
> +#define PWR_BASE__INST4_SEG1 0
> +#define PWR_BASE__INST4_SEG2 0
> +#define PWR_BASE__INST4_SEG3 0
> +#define PWR_BASE__INST4_SEG4 0
> +
> +#define CLK_BASE__INST0_SEG0 0x00016C00
> +#define CLK_BASE__INST0_SEG1 0
> +#define CLK_BASE__INST0_SEG2 0
> +#define CLK_BASE__INST0_SEG3 0
> +#define CLK_BASE__INST0_SEG4 0
> +
> +#define CLK_BASE__INST1_SEG0 0x00016E00
> +#define CLK_BASE__INST1_SEG1 0
> +#define CLK_BASE__INST1_SEG2 0
> +#define CLK_BASE__INST1_SEG3 0
> +#define CLK_BASE__INST1_SEG4 0
> +
> +#define CLK_BASE__INST2_SEG0 0x00017000
> +#define CLK_BASE__INST2_SEG1 0
> +#define CLK_BASE__INST2_SEG2 0
> +#define CLK_BASE__INST2_SEG3 0
> +#define CLK_BASE__INST2_SEG4 0
> +
> +#define CLK_BASE__INST3_SEG0 0x00017200
> +#define CLK_BASE__INST3_SEG1 0
> +#define CLK_BASE__INST3_SEG2 0
> +#define CLK_BASE__INST3_SEG3 0
> +#define CLK_BASE__INST3_SEG4 0
> +
> +#define CLK_BASE__INST4_SEG0 0x00017E00
> +#define CLK_BASE__INST4_SEG1 0
> +#define CLK_BASE__INST4_SEG2 0
> +#define CLK_BASE__INST4_SEG3 0
> +#define CLK_BASE__INST4_SEG4 0
> +
> +#define FUSE_BASE__INST0_SEG0 0x00017400
> +#define FUSE_BASE__INST0_SEG1 0
> +#define FUSE_BASE__INST0_SEG2 0
> +#define FUSE_BASE__INST0_SEG3 0
> +#define FUSE_BASE__INST0_SEG4 0
> +
> +#define FUSE_BASE__INST1_SEG0 0
> +#define FUSE_BASE__INST1_SEG1 0
> +#define FUSE_BASE__INST1_SEG2 0
> +#define FUSE_BASE__INST1_SEG3 0
> +#define FUSE_BASE__INST1_SEG4 0
> +
> +#define FUSE_BASE__INST2_SEG0 0
> +#define FUSE_BASE__INST2_SEG1 0
> +#define FUSE_BASE__INST2_SEG2 0
> +#define FUSE_BASE__INST2_SEG3 0
> +#define FUSE_BASE__INST2_SEG4 0
> +
> +#define FUSE_BASE__INST3_SEG0 0
> +#define FUSE_BASE__INST3_SEG1 0
> +#define FUSE_BASE__INST3_SEG2 0
> +#define FUSE_BASE__INST3_SEG3 0
> +#define FUSE_BASE__INST3_SEG4 0
> +
> +#define FUSE_BASE__INST4_SEG0 0
> +#define FUSE_BASE__INST4_SEG1 0
> +#define FUSE_BASE__INST4_SEG2 0
> +#define FUSE_BASE__INST4_SEG3 0
> +#define FUSE_BASE__INST4_SEG4 0
> +
> +
> +#endif
> +
>
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next prev parent reply other threads:[~2017-11-27 18:54 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-27 18:30 [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file Shaoyun Liu
[not found] ` <1511807458-27102-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org>
2017-11-27 18:54 ` Tom St Denis [this message]
[not found] ` <a831909b-4381-1a63-fba3-0eb816fa5e61-5C7GfCeVMHo@public.gmane.org>
2017-11-27 19:04 ` Liu, Shaoyun
2017-11-27 19:17 ` Christian König
[not found] ` <2db922e4-fe49-7499-38f1-a3b2c8e07cf5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-11-27 19:29 ` Liu, Shaoyun
2017-11-27 19:37 Koenig, Christian
[not found] ` <2a0a3687-0207-4ea0-bb2c-20750a1d2bb3-2ueSQiBKiTY7tOexoI0I+QC/G2K4zDHf@public.gmane.org>
2017-11-27 20:01 ` Felix Kuehling
[not found] ` <702bfce6-78ef-0284-6306-f4b3366d34f7-5C7GfCeVMHo@public.gmane.org>
2017-11-27 20:44 ` Christian König
[not found] ` <ec783d5b-74a5-07e8-6bb4-5c930e56a718-5C7GfCeVMHo@public.gmane.org>
2017-11-27 20:56 ` Alex Deucher
[not found] ` <CADnq5_M55-qJEwfVGvkxpajePPxK1fePzG57ZTjCLVBQuddf6w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-11-27 21:24 ` Liu, Shaoyun
2017-11-27 21:28 ` Christian König
[not found] ` <cca23fad-52d4-8c49-d2b1-e7ed1bde7b39-5C7GfCeVMHo@public.gmane.org>
2017-11-27 22:30 ` Tom St Denis
[not found] ` <fefe3e0b-91d8-39dc-2d34-9a795cf61274-5C7GfCeVMHo@public.gmane.org>
2017-11-28 9:40 ` Christian König
2017-11-27 22:40 ` Alex Deucher
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