From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming Date: Fri, 19 Apr 2019 16:02:10 +0000 Message-ID: References: <20190419071026.32370-1-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0050346758==" Return-path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2521B892B6 for ; Fri, 19 Apr 2019 16:02:12 +0000 (UTC) In-Reply-To: <20190419071026.32370-1-imre.deak@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "intel-gfx@lists.freedesktop.org" , "Deak, Imre" Cc: "De Marchi, Lucas" List-Id: intel-gfx@lists.freedesktop.org --===============0050346758== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-IUwbpfD9snpS7ZHtTrcQ" --=-IUwbpfD9snpS7ZHtTrcQ Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote: > Fix the order of lane, port parameters passed to the register macro. >=20 > Note that this was already partly fixed by commit > 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right > parameters order") >=20 > Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically > consistent") > Cc: Jos=C3=A9 Roberto de Souza > Cc: Lucas De Marchi > Cc: Aditya Swarup > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++---------- > 1 file changed, 8 insertions(+), 10 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > b/drivers/gpu/drm/i915/intel_ddi.c > index 24f9106efcc6..f181c26f62fd 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2905,21 +2905,20 @@ static void > icl_enable_phy_clock_gating(struct intel_digital_port *dig_port) > struct drm_i915_private *dev_priv =3D to_i915(dig_port- > >base.base.dev); > enum port port =3D dig_port->base.port; > enum tc_port tc_port =3D intel_port_to_tc(dev_priv, port); > - i915_reg_t mg_regs[2] =3D { MG_DP_MODE(0, port), MG_DP_MODE(1, > port) }; > u32 val; > - int i; > + int ln; > =20 > if (tc_port =3D=3D PORT_TC_NONE) > return; > =20 > - for (i =3D 0; i < ARRAY_SIZE(mg_regs); i++) { > - val =3D I915_READ(mg_regs[i]); > + for (ln =3D 0; ln < 2; ln++) { > + val =3D I915_READ(MG_DP_MODE(ln, port)); > val |=3D MG_DP_MODE_CFG_TR2PWR_GATING | > MG_DP_MODE_CFG_TRPWR_GATING | > MG_DP_MODE_CFG_CLNPWR_GATING | > MG_DP_MODE_CFG_DIGPWR_GATING | > MG_DP_MODE_CFG_GAONPWR_GATING; > - I915_WRITE(mg_regs[i], val); > + I915_WRITE(MG_DP_MODE(ln, port), val); > } > =20 > val =3D I915_READ(MG_MISC_SUS0(tc_port)); > @@ -2938,21 +2937,20 @@ static void > icl_disable_phy_clock_gating(struct intel_digital_port *dig_port) > struct drm_i915_private *dev_priv =3D to_i915(dig_port- > >base.base.dev); > enum port port =3D dig_port->base.port; > enum tc_port tc_port =3D intel_port_to_tc(dev_priv, port); > - i915_reg_t mg_regs[2] =3D { MG_DP_MODE(port, 0), MG_DP_MODE(port, > 1) }; I would split this fix from the change dropping mg_regs or at least tell that while you were fixing it you changed the way it reads each MG_DP_MODE line. > u32 val; > - int i; > + int ln; > =20 > if (tc_port =3D=3D PORT_TC_NONE) > return; > =20 > - for (i =3D 0; i < ARRAY_SIZE(mg_regs); i++) { > - val =3D I915_READ(mg_regs[i]); > + for (ln =3D 0; ln < 2; ln++) { > + val =3D I915_READ(MG_DP_MODE(ln, port)); > val &=3D ~(MG_DP_MODE_CFG_TR2PWR_GATING | > MG_DP_MODE_CFG_TRPWR_GATING | > MG_DP_MODE_CFG_CLNPWR_GATING | > MG_DP_MODE_CFG_DIGPWR_GATING | > MG_DP_MODE_CFG_GAONPWR_GATING); > - I915_WRITE(mg_regs[i], val); > + I915_WRITE(MG_DP_MODE(ln, port), val); > } > =20 > val =3D I915_READ(MG_MISC_SUS0(tc_port)); --=-IUwbpfD9snpS7ZHtTrcQ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAly58QEACgkQVenbO/mO WklYCgf8DW17RBlwGxb9PpyZmmRTHN66C5yFp2TE8acCnJPyzPw84Mgf4E0zfXuV jtbWMeX+kSuz2cK1P1TWrHoOrSD0G8xUNG/3GwSoq8S7o0wcN8C2kySxRA6lPBzI a6Dqic++q7Y0WzwJK+yeWYjOyeOAK+aBUb846dn9b0E/SyfLBUAtohzzIUqZgksG S58q8sREE3H0hJfd221FQO6DOp91v9pidICtRT5BoMtkobb5WX3uPGH2G2X1DpOb nxNf9PoeMcYqCINP60mOdsIddhoE7JFDn7jzh/Gkkpqa+DRlI45qOSgcAh8VGZek EqHie+DR6DlftX92RRE0hhSqG3QA4g== =WRbD -----END PGP SIGNATURE----- --=-IUwbpfD9snpS7ZHtTrcQ-- --===============0050346758== Content-Type: text/plain; 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