From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00C73C433DF for ; Mon, 12 Oct 2020 11:52:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A51792074A for ; Mon, 12 Oct 2020 11:52:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="rYAvjK/l" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388408AbgJLLwX (ORCPT ); Mon, 12 Oct 2020 07:52:23 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:42554 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388299AbgJLLwX (ORCPT ); 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Mon, 12 Oct 2020 06:52:11 -0500 Received: from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 09CBq8O9082144; Mon, 12 Oct 2020 06:52:09 -0500 Subject: Re: [PATCH v2 2/2] irqchip/ti-sci-inta: Add support for unmapped event handling To: Marc Zyngier CC: , , , , , , , , , References: <20200930074559.18028-1-peter.ujfalusi@ti.com> <20200930074559.18028-3-peter.ujfalusi@ti.com> <3dc2f27f-0a41-b538-11ac-970ad4310ccb@ti.com> <714738536a5566c511e83dc424e94bf7@kernel.org> <3e9974b8-c0ab-9de4-9b51-541c2093c42a@ti.com> <7e66c03285db40c6ce38b951b87bcb45@kernel.org> From: Peter Ujfalusi Message-ID: Date: Mon, 12 Oct 2020 14:52:33 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.3.2 MIME-Version: 1.0 In-Reply-To: <7e66c03285db40c6ce38b951b87bcb45@kernel.org> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/10/2020 10.31, Marc Zyngier wrote: > On 2020-10-09 09:58, Peter Ujfalusi wrote: >> Marc, >> > > [...] > >> The design of irqchip/irq-ti-sci-inta.c, soc/ti/ti_sci_inta_msi.c and >> irqchip/irq-ti-sci-intr.c created to handle the interrupt needs present >> in K3 devices with NAVSS. >> DMSS of newer K3 devices extends and simplifies the NAVSS components and >> a big part of that change was done with the INTA and DMAs. >> System Firmware also changed to adopt to these changes. >> >> As an example, let's assume that we want an interrupt from a ring. >> The high level of the events in this case are: >> >> NAVSS: >> 1.1 ring generates an internal signal (up or down) >> 1.2 the ringacc will send a (mapped) Global Event to INTA >> 1.3 When INTA receives the global event, it will signal it's outgoing >>     VINT to INTR >> 1.4 INTR will trigger a host interrupt. >> >> DMSS >> 1.1 ring generates an internal signal (up or down) >> 1.2 the DMA (ring is now part of the DMA) will send an unmapped event to >>     INTA >> 1.3 When INTA receives the unmapped event, it will send a (mapped) >>     Global Event to itself >> 1.4 When INTA receives the global event, it will signal it's outgoing >>     VINT to INTR >> 1.5 INTR will trigger a host interrupt. >> >> The API from sysfw is the same to configure the global events and VINT, >> but we need to use the INTA's tisci device identification number to let >> sysfw know that the Global event number can be programmed into INTA's >> unmapped event steering register. The DMA no longer have this register, >> it sends unmapped event to INTA. >> >> The unmapped event number is fixed per sources, they will arrive at the >> specific unmapped event configuration register of INTA. >> >> INTA itself does not know which source are allocated to be used by >> Linux, the allocation is for the DMA resources and only the DMA driver >> knows which channels, rings, flows can be used and can ask the INTA MSI >> domain to create interrupts for those. >> >> By handling the ti,unmapped-event-sources the INTA driver can make >> decision on the correct tisci dev_id to be used for the sysfw API to >> where the global event must be configured and the client drivers does >> not need to know how things are working under the hood. >> >> There are components in DMSS which use is exactly how they worked within >> NAVSS, they are not using unmapped events. Ringacc comes to mind first. >> >> I can add a comment block to explain the nature of unmapped events and >> the reason why we need to do what we do. >> >> Would this be acceptable? > > That'd be useful, as long as it is shorter than the above. OK, I will send an update next week after I'm back. - Péter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. 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from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 09CBq8O9082144; Mon, 12 Oct 2020 06:52:09 -0500 Subject: Re: [PATCH v2 2/2] irqchip/ti-sci-inta: Add support for unmapped event handling To: Marc Zyngier References: <20200930074559.18028-1-peter.ujfalusi@ti.com> <20200930074559.18028-3-peter.ujfalusi@ti.com> <3dc2f27f-0a41-b538-11ac-970ad4310ccb@ti.com> <714738536a5566c511e83dc424e94bf7@kernel.org> <3e9974b8-c0ab-9de4-9b51-541c2093c42a@ti.com> <7e66c03285db40c6ce38b951b87bcb45@kernel.org> From: Peter Ujfalusi Message-ID: Date: Mon, 12 Oct 2020 14:52:33 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.3.2 MIME-Version: 1.0 In-Reply-To: <7e66c03285db40c6ce38b951b87bcb45@kernel.org> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: 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YW5kbGUgdGhlIGludGVycnVwdCBuZWVkcyBwcmVzZW50Cj4+IGluIEszIGRldmljZXMgd2l0aCBO QVZTUy4KPj4gRE1TUyBvZiBuZXdlciBLMyBkZXZpY2VzIGV4dGVuZHMgYW5kIHNpbXBsaWZpZXMg dGhlIE5BVlNTIGNvbXBvbmVudHMgYW5kCj4+IGEgYmlnIHBhcnQgb2YgdGhhdCBjaGFuZ2Ugd2Fz IGRvbmUgd2l0aCB0aGUgSU5UQSBhbmQgRE1Bcy4KPj4gU3lzdGVtIEZpcm13YXJlIGFsc28gY2hh bmdlZCB0byBhZG9wdCB0byB0aGVzZSBjaGFuZ2VzLgo+Pgo+PiBBcyBhbiBleGFtcGxlLCBsZXQn cyBhc3N1bWUgdGhhdCB3ZSB3YW50IGFuIGludGVycnVwdCBmcm9tIGEgcmluZy4KPj4gVGhlIGhp Z2ggbGV2ZWwgb2YgdGhlIGV2ZW50cyBpbiB0aGlzIGNhc2UgYXJlOgo+Pgo+PiBOQVZTUzoKPj4g MS4xIHJpbmcgZ2VuZXJhdGVzIGFuIGludGVybmFsIHNpZ25hbCAodXAgb3IgZG93bikKPj4gMS4y IHRoZSByaW5nYWNjIHdpbGwgc2VuZCBhIChtYXBwZWQpIEdsb2JhbCBFdmVudCB0byBJTlRBCj4+ IDEuMyBXaGVuIElOVEEgcmVjZWl2ZXMgdGhlIGdsb2JhbCBldmVudCwgaXQgd2lsbCBzaWduYWwg aXQncyBvdXRnb2luZwo+PiDCoMKgwqAgVklOVCB0byBJTlRSCj4+IDEuNCBJTlRSIHdpbGwgdHJp Z2dlciBhIGhvc3QgaW50ZXJydXB0Lgo+Pgo+PiBETVNTCj4+IDEuMSByaW5nIGdlbmVyYXRlcyBh biBpbnRlcm5hbCBzaWduYWwgKHVwIG9yIGRvd24pCj4+IDEuMiB0aGUgRE1BIChyaW5nIGlzIG5v dyBwYXJ0IG9mIHRoZSBETUEpIHdpbGwgc2VuZCBhbiB1bm1hcHBlZCBldmVudCB0bwo+PiDCoMKg wqAgSU5UQQo+PiAxLjMgV2hlbiBJTlRBIHJlY2VpdmVzIHRoZSB1bm1hcHBlZCBldmVudCwgaXQg d2lsbCBzZW5kIGEgKG1hcHBlZCkKPj4gwqDCoMKgIEdsb2JhbCBFdmVudCB0byBpdHNlbGYKPj4g MS40IFdoZW4gSU5UQSByZWNlaXZlcyB0aGUgZ2xvYmFsIGV2ZW50LCBpdCB3aWxsIHNpZ25hbCBp dCdzIG91dGdvaW5nCj4+IMKgwqDCoCBWSU5UIHRvIElOVFIKPj4gMS41IElOVFIgd2lsbCB0cmln Z2VyIGEgaG9zdCBpbnRlcnJ1cHQuCj4+Cj4+IFRoZSBBUEkgZnJvbSBzeXNmdyBpcyB0aGUgc2Ft ZSB0byBjb25maWd1cmUgdGhlIGdsb2JhbCBldmVudHMgYW5kIFZJTlQsCj4+IGJ1dCB3ZSBuZWVk IHRvIHVzZSB0aGUgSU5UQSdzIHRpc2NpIGRldmljZSBpZGVudGlmaWNhdGlvbiBudW1iZXIgdG8g bGV0Cj4+IHN5c2Z3IGtub3cgdGhhdCB0aGUgR2xvYmFsIGV2ZW50IG51bWJlciBjYW4gYmUgcHJv Z3JhbW1lZCBpbnRvIElOVEEncwo+PiB1bm1hcHBlZCBldmVudCBzdGVlcmluZyByZWdpc3Rlci4g VGhlIERNQSBubyBsb25nZXIgaGF2ZSB0aGlzIHJlZ2lzdGVyLAo+PiBpdCBzZW5kcyB1bm1hcHBl ZCBldmVudCB0byBJTlRBLgo+Pgo+PiBUaGUgdW5tYXBwZWQgZXZlbnQgbnVtYmVyIGlzIGZpeGVk IHBlciBzb3VyY2VzLCB0aGV5IHdpbGwgYXJyaXZlIGF0IHRoZQo+PiBzcGVjaWZpYyB1bm1hcHBl ZCBldmVudCBjb25maWd1cmF0aW9uIHJlZ2lzdGVyIG9mIElOVEEuCj4+Cj4+IElOVEEgaXRzZWxm IGRvZXMgbm90IGtub3cgd2hpY2ggc291cmNlIGFyZSBhbGxvY2F0ZWQgdG8gYmUgdXNlZCBieQo+ PiBMaW51eCwgdGhlIGFsbG9jYXRpb24gaXMgZm9yIHRoZSBETUEgcmVzb3VyY2VzIGFuZCBvbmx5 IHRoZSBETUEgZHJpdmVyCj4+IGtub3dzIHdoaWNoIGNoYW5uZWxzLCByaW5ncywgZmxvd3MgY2Fu IGJlIHVzZWQgYW5kIGNhbiBhc2sgdGhlIElOVEEgTVNJCj4+IGRvbWFpbiB0byBjcmVhdGUgaW50 ZXJydXB0cyBmb3IgdGhvc2UuCj4+Cj4+IEJ5IGhhbmRsaW5nIHRoZSB0aSx1bm1hcHBlZC1ldmVu dC1zb3VyY2VzIHRoZSBJTlRBIGRyaXZlciBjYW4gbWFrZQo+PiBkZWNpc2lvbiBvbiB0aGUgY29y cmVjdCB0aXNjaSBkZXZfaWQgdG8gYmUgdXNlZCBmb3IgdGhlIHN5c2Z3IEFQSSB0bwo+PiB3aGVy ZSB0aGUgZ2xvYmFsIGV2ZW50IG11c3QgYmUgY29uZmlndXJlZCBhbmQgdGhlIGNsaWVudCBkcml2 ZXJzIGRvZXMKPj4gbm90IG5lZWQgdG8ga25vdyBob3cgdGhpbmdzIGFyZSB3b3JraW5nIHVuZGVy IHRoZSBob29kLgo+Pgo+PiBUaGVyZSBhcmUgY29tcG9uZW50cyBpbiBETVNTIHdoaWNoIHVzZSBp cyBleGFjdGx5IGhvdyB0aGV5IHdvcmtlZCB3aXRoaW4KPj4gTkFWU1MsIHRoZXkgYXJlIG5vdCB1 c2luZyB1bm1hcHBlZCBldmVudHMuIFJpbmdhY2MgY29tZXMgdG8gbWluZCBmaXJzdC4KPj4KPj4g SSBjYW4gYWRkIGEgY29tbWVudCBibG9jayB0byBleHBsYWluIHRoZSBuYXR1cmUgb2YgdW5tYXBw ZWQgZXZlbnRzIGFuZAo+PiB0aGUgcmVhc29uIHdoeSB3ZSBuZWVkIHRvIGRvIHdoYXQgd2UgZG8u Cj4+Cj4+IFdvdWxkIHRoaXMgYmUgYWNjZXB0YWJsZT8KPiAKPiBUaGF0J2QgYmUgdXNlZnVsLCBh cyBsb25nIGFzIGl0IGlzIHNob3J0ZXIgdGhhbiB0aGUgYWJvdmUuCgpPSywgSSB3aWxsIHNlbmQg YW4gdXBkYXRlIG5leHQgd2VlayBhZnRlciBJJ20gYmFjay4KCgotIFDDqXRlcgoKVGV4YXMgSW5z dHJ1bWVudHMgRmlubGFuZCBPeSwgUG9ya2thbGFua2F0dSAyMiwgMDAxODAgSGVsc2lua2kuClkt dHVubnVzL0J1c2luZXNzIElEOiAwNjE1NTIxLTQuIEtvdGlwYWlra2EvRG9taWNpbGU6IEhlbHNp bmtpCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51 eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVh ZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1h cm0ta2VybmVsCg==