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Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [Patch V1 3/4] memory: tegra: add mc-err support for T186 Content-Language: en-US To: Dmitry Osipenko , , , , , CC: , References: <1641926750-27544-1-git-send-email-amhetre@nvidia.com> <1641926750-27544-4-git-send-email-amhetre@nvidia.com> From: Ashish Mhetre In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c8ace445-263f-4116-dcdc-08d9db292cdd X-MS-TrafficTypeDiagnostic: MN2PR12MB3983:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: P4Q3i9jTa0zzjUkHGw06poCGFB8o+y7lqqC/KvH+bU3Vqnn/WAPSq8zAb01LXUCkRXNULzbi5MeIG4IsZeS4mTBifRopI1gtPWOMwKORDckBKfMS9ebVyGp1U5JfYqToHiB6QpHKENS+KLtzJgnqRvlmv438oAeBuKZ9jnMIV6eNDhG+iZb+EoU68Xww/QYOeiCtfU1YYhDg6AGRpMF2oQXbv6Le+UvHsC+ZHTmrAn58sIQJmW5pFxB4bRYr/LAb+49eRXXzocd6Vef0DEAokCckadPvS/E/872V9Bj29ZDZM3P1w41a6xwyAPLjLJMpscV4XGG3roMJy0PX3EjJL3qrw9KBLhQkcDO3W+yl5/ZmYBq6kFkHZ0ypBMvgFdvBGBlgU95yO0+gMuE15NMKI1AftWDCKq5w7cYU+eG4gm+vXKuoHHc7GtkW9ZJPTRBcD4Zv6jTv5tupBzF1rHzVnuKFHU30psWoLQ6/CxsnoZjxFbW2hRExjS7MqD4Zt+didtGV+ggHTcLjK3E6oUK3sAUWRyV30TTFkxLXnkoW6nSAXCxHd/WUfixrwPA1uyR/d6KKi8Yqe9DA01CyTWeEWzQvGr0P511fu2LVh+fmv3M+FbUGN4Kf44le7dOoFkQ4tAL8mgSk2GR8OfKeTu6BPYCPTWPJuRbLuE1yPGS8tb4M4QOamFgkW8mCYUXtioMLJgdbTFD4aOM87inSaYXCPCekNt1NxkPRMdDyZ6M7ymXf7kSRoEyAo9j7tY0lN2YR6+W9W6mX8DHpLOvHYXrwrTpaQ3OVkn7uLqf3cQzAWsUIkZZofsg1RmVfa/ANw0NXkTX+o3FlWUhO+C3gDhBRgg== X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(4636009)(36840700001)(40470700002)(46966006)(31686004)(70206006)(5660300002)(4326008)(70586007)(426003)(2616005)(86362001)(53546011)(110136005)(316002)(107886003)(16576012)(36756003)(8936002)(26005)(31696002)(336012)(82310400004)(47076005)(16526019)(186003)(8676002)(508600001)(36860700001)(6666004)(81166007)(40460700001)(83380400001)(2906002)(54906003)(356005)(36900700001)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2022 08:53:34.0796 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c8ace445-263f-4116-dcdc-08d9db292cdd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3983 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On 1/12/2022 4:31 PM, Dmitry Osipenko wrote: > External email: Use caution opening links or attachments > > > 11.01.2022 21:45, Ashish Mhetre пишет: >> Add all mc-errors supported by T186. >> Implement mc interrupt handling routine for T186. >> >> Signed-off-by: Ashish Mhetre >> --- >> drivers/memory/tegra/mc.h | 17 +++++++ >> drivers/memory/tegra/tegra186.c | 100 ++++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 117 insertions(+) >> >> diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h >> index 2d4f495..7817492 100644 >> --- a/drivers/memory/tegra/mc.h >> +++ b/drivers/memory/tegra/mc.h >> @@ -44,6 +44,15 @@ >> #define MC_TIMING_CONTROL_DBG 0xf8 >> #define MC_TIMING_CONTROL 0xfc >> > > this empty line is unnecessary > I'll fix this in next version. >> +#define MC_ERR_VPR_STATUS 0x654 >> +#define MC_ERR_VPR_ADR 0x658 >> +#define MC_ERR_SEC_STATUS 0x67c >> +#define MC_ERR_SEC_ADR 0x680 >> +#define MC_ERR_MTS_STATUS 0x9b0 >> +#define MC_ERR_MTS_ADR 0x9b4 >> +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 >> +#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 >> + >> #define MC_INT_DECERR_ROUTE_SANITY BIT(20) >> #define MC_INT_WCAM_ERR BIT(19) >> #define MC_INT_SCRUB_ECC_WR_ACK BIT(18) >> @@ -159,6 +168,14 @@ extern const struct tegra_mc_ops tegra186_mc_ops; >> extern const char * const tegra_mc_status_names[32]; >> extern const char * const tegra_mc_error_names[8]; >> >> +struct tegra_mc_error { >> + u32 int_bit; >> + const char *msg; >> + u32 status_reg; >> + u32 addr_reg; >> + u32 addr_reg_hi; >> +}; >> + >> /* >> * These IDs are for internal use of Tegra ICC drivers. The ID numbers are >> * chosen such that they don't conflict with the device-tree ICC node IDs. >> diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c >> index 6766cc4..4f3ae71 100644 >> --- a/drivers/memory/tegra/tegra186.c >> +++ b/drivers/memory/tegra/tegra186.c >> @@ -146,8 +146,107 @@ static void tegra186_mc_clear_interrupt(struct tegra_mc *mc) >> mc_writel(mc, MC_INTSTATUS_CLEAR, MC_INTSTATUS); >> } >> >> +static const struct tegra_mc_error int_mc_errors[] = { >> + { >> + .int_bit = MC_INT_DECERR_EMEM, >> + .msg = "EMEM address decode error", >> + .status_reg = MC_ERR_STATUS, >> + .addr_reg = MC_ERR_ADR, >> + }, >> + { >> + .int_bit = MC_INT_SECURITY_VIOLATION, >> + .msg = "non secure access to secure region", >> + .status_reg = MC_ERR_STATUS, >> + .addr_reg = MC_ERR_ADR, >> + }, >> + { >> + .int_bit = MC_INT_DECERR_VPR, >> + .msg = "MC request violates VPR requirements", >> + .status_reg = MC_ERR_VPR_STATUS, >> + .addr_reg = MC_ERR_VPR_ADR, >> + }, > > I see that these VPR registers present on all SoCs starting with T124. > It doesn't look like you need the separate IRQ handlers at all, instead > please extend the common T30 handler. For example, you may add a > switch-case statements to handle those T124+ specific bits differently. > > static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) > { > ... > switch (bit) { > case MC_INT_DECERR_VPR: > status_reg = MC_ERR_VPR_STATUS; > addr_reg = MC_ERR_VPR_ADR; > break; > ... > default: > status_reg = MC_ERR_STATUS; > addr_reg = MC_ERR_ADR; > } > > value = mc_readl(mc, status_reg); > ... > > value = mc_readl(mc, addr_reg); Okay. I'll use same handler as Tegra30 with additional Tegra186 onward bits. Also, shall I change name of tegra30_mc_handle_irq() to tegra_mc_handle_irq() as we are using it across all Tegra SOCs ?