From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Tue, 12 Mar 2019 11:44:25 +0100 Subject: [U-Boot] [PATCH 03/10] ddr: altera: s10: Add multiple memory banks support In-Reply-To: <1552379474-12867-4-git-send-email-ley.foon.tan@intel.com> References: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> <1552379474-12867-4-git-send-email-ley.foon.tan@intel.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 3/12/19 9:31 AM, Ley Foon Tan wrote: > Setup bank start address and size based on total SDRAM > memory size calculated from hardware. Update sdram_size_check() > to support multiple banks. > > Stratix10 supports up to 2 memory banks. > > Bank 0: Address 0, size 2GB > Bank 1: Address 0x100000000, size 124GB > > Signed-off-by: Dalon Westergreen > Signed-off-by: Ley Foon Tan Shouldn't Quartus generate some sort of DT which gives you all the DRAM layout information ? Then you won't need any of this CONFIG_NR_DRAM_BANKS stuff, but you would be able to extract such info from DT and apply the sanity check only on DRAM you know exists. -- Best regards, Marek Vasut