From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E27C4C65BA7 for ; Fri, 5 Oct 2018 17:03:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A5F2B2147D for ; Fri, 5 Oct 2018 17:03:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A5F2B2147D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729341AbeJFACp (ORCPT ); Fri, 5 Oct 2018 20:02:45 -0400 Received: from mga03.intel.com ([134.134.136.65]:61174 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728214AbeJFACp (ORCPT ); Fri, 5 Oct 2018 20:02:45 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Oct 2018 10:03:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,345,1534834800"; d="scan'208";a="78790390" Received: from 2b52.sc.intel.com ([143.183.136.147]) by orsmga007.jf.intel.com with ESMTP; 05 Oct 2018 10:03:07 -0700 Message-ID: Subject: Re: [RFC PATCH v4 3/9] x86/cet/ibt: Add IBT legacy code bitmap allocation function From: Yu-cheng Yu To: Andy Lutomirski Cc: Eugene Syromiatnikov , x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue Date: Fri, 05 Oct 2018 09:58:24 -0700 In-Reply-To: <5BF3AE8F-CC2A-4160-9FF6-FEA171A76371@amacapital.net> References: <20180921150553.21016-1-yu-cheng.yu@intel.com> <20180921150553.21016-4-yu-cheng.yu@intel.com> <20181003195702.GF32759@asgard.redhat.com> <5BF3AE8F-CC2A-4160-9FF6-FEA171A76371@amacapital.net> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.1-2 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2018-10-05 at 09:28 -0700, Andy Lutomirski wrote: > > On Oct 5, 2018, at 9:13 AM, Yu-cheng Yu wrote: > > > > > On Wed, 2018-10-03 at 21:57 +0200, Eugene Syromiatnikov wrote: > > > > On Fri, Sep 21, 2018 at 08:05:47AM -0700, Yu-cheng Yu wrote: > > > > Indirect branch tracking provides an optional legacy code bitmap > > > > that indicates locations of non-IBT compatible code. When set, > > > > each bit in the bitmap represents a page in the linear address is > > > > legacy code. > > > > > > > > We allocate the bitmap only when the application requests it. > > > > Most applications do not need the bitmap. > > > > > > > > Signed-off-by: Yu-cheng Yu > > > > --- > > > > arch/x86/kernel/cet.c | 45 +++++++++++++++++++++++++++++++++++++++++++ > > > > 1 file changed, 45 insertions(+) > > > > > > > > diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c > > > > index 6adfe795d692..a65d9745af08 100644 > > > > --- a/arch/x86/kernel/cet.c > > > > +++ b/arch/x86/kernel/cet.c > > > > @@ -314,3 +314,48 @@ void cet_disable_ibt(void) > > > > wrmsrl(MSR_IA32_U_CET, r); > > > > current->thread.cet.ibt_enabled = 0; > > > > } > > > > + > > > > +int cet_setup_ibt_bitmap(void) > > > > +{ > > > > + u64 r; > > > > + unsigned long bitmap; > > > > + unsigned long size; > > > > + > > > > + if (!cpu_feature_enabled(X86_FEATURE_IBT)) > > > > + return -EOPNOTSUPP; > > > > + > > > > + if (!current->thread.cet.ibt_bitmap_addr) { > > > > + /* > > > > + * Calculate size and put in thread header. > > > > + * may_expand_vm() needs this information. > > > > + */ > > > > + size = TASK_SIZE / PAGE_SIZE / BITS_PER_BYTE; > > > > > > TASK_SIZE_MAX is likely needed here, as an application can easily switch > > > between long an 32-bit protected mode. And then the case of a CPU that > > > doesn't support 5LPT. > > > > If we had calculated bitmap size from TASK_SIZE_MAX, all 32-bit apps would > > have > > failed the allocation for bitmap size > TASK_SIZE. Please see values below, > > which is printed from the current code. > > > > Yu-cheng > > > > > > x64: > > TASK_SIZE_MAX = 0000 7fff ffff f000 > > TASK_SIZE = 0000 7fff ffff f000 > > bitmap size = 0000 0000 ffff ffff > > > > x32: > > TASK_SIZE_MAX = 0000 7fff ffff f000 > > TASK_SIZE = 0000 0000 ffff e000 > > bitmap size = 0000 0000 0001 ffff > > > > I haven’t followed all the details here, but I have a general policy of > objecting to any new use of TASK_SIZE. If you really really need to depend on > 32-bitness in new code, please figure out what exactly you mean by “32-bit” > and use an explicit check. The explicit check would be: test_thread_flag(TIF_ADDR32) ? IA32_PAGE_OFFSET : TASK_SIZE_MAX which is the same as TASK_SIZE. Or, do we want a new macro? #define IBT_BITMAP_SIZE (test_thread_flag(TIF_ADDR32) ? \ (IA32_PAGE_OFFSET / PAGE_SIZE / BITS_PER_BYTE) : \ (TASK_SIZE_MAX / PAGE_SIZE / BITS_PER_BYTE)) Yu-cheng From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu-cheng Yu Subject: Re: [RFC PATCH v4 3/9] x86/cet/ibt: Add IBT legacy code bitmap allocation function Date: Fri, 05 Oct 2018 09:58:24 -0700 Message-ID: References: <20180921150553.21016-1-yu-cheng.yu@intel.com> <20180921150553.21016-4-yu-cheng.yu@intel.com> <20181003195702.GF32759@asgard.redhat.com> <5BF3AE8F-CC2A-4160-9FF6-FEA171A76371@amacapital.net> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <5BF3AE8F-CC2A-4160-9FF6-FEA171A76371@amacapital.net> Sender: linux-kernel-owner@vger.kernel.org To: Andy Lutomirski Cc: Eugene Syromiatnikov , x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek Peter List-Id: linux-api@vger.kernel.org On Fri, 2018-10-05 at 09:28 -0700, Andy Lutomirski wrote: > > On Oct 5, 2018, at 9:13 AM, Yu-cheng Yu wrote: > > > > > On Wed, 2018-10-03 at 21:57 +0200, Eugene Syromiatnikov wrote: > > > > On Fri, Sep 21, 2018 at 08:05:47AM -0700, Yu-cheng Yu wrote: > > > > Indirect branch tracking provides an optional legacy code bitmap > > > > that indicates locations of non-IBT compatible code. When set, > > > > each bit in the bitmap represents a page in the linear address is > > > > legacy code. > > > > > > > > We allocate the bitmap only when the application requests it. > > > > Most applications do not need the bitmap. > > > > > > > > Signed-off-by: Yu-cheng Yu > > > > --- > > > > arch/x86/kernel/cet.c | 45 +++++++++++++++++++++++++++++++++++++++++++ > > > > 1 file changed, 45 insertions(+) > > > > > > > > diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c > > > > index 6adfe795d692..a65d9745af08 100644 > > > > --- a/arch/x86/kernel/cet.c > > > > +++ b/arch/x86/kernel/cet.c > > > > @@ -314,3 +314,48 @@ void cet_disable_ibt(void) > > > > wrmsrl(MSR_IA32_U_CET, r); > > > > current->thread.cet.ibt_enabled = 0; > > > > } > > > > + > > > > +int cet_setup_ibt_bitmap(void) > > > > +{ > > > > + u64 r; > > > > + unsigned long bitmap; > > > > + unsigned long size; > > > > + > > > > + if (!cpu_feature_enabled(X86_FEATURE_IBT)) > > > > + return -EOPNOTSUPP; > > > > + > > > > + if (!current->thread.cet.ibt_bitmap_addr) { > > > > + /* > > > > + * Calculate size and put in thread header. > > > > + * may_expand_vm() needs this information. > > > > + */ > > > > + size = TASK_SIZE / PAGE_SIZE / BITS_PER_BYTE; > > > > > > TASK_SIZE_MAX is likely needed here, as an application can easily switch > > > between long an 32-bit protected mode. And then the case of a CPU that > > > doesn't support 5LPT. > > > > If we had calculated bitmap size from TASK_SIZE_MAX, all 32-bit apps would > > have > > failed the allocation for bitmap size > TASK_SIZE. Please see values below, > > which is printed from the current code. > > > > Yu-cheng > > > > > > x64: > > TASK_SIZE_MAX = 0000 7fff ffff f000 > > TASK_SIZE = 0000 7fff ffff f000 > > bitmap size = 0000 0000 ffff ffff > > > > x32: > > TASK_SIZE_MAX = 0000 7fff ffff f000 > > TASK_SIZE = 0000 0000 ffff e000 > > bitmap size = 0000 0000 0001 ffff > > > > I haven’t followed all the details here, but I have a general policy of > objecting to any new use of TASK_SIZE. If you really really need to depend on > 32-bitness in new code, please figure out what exactly you mean by “32-bit” > and use an explicit check. The explicit check would be: test_thread_flag(TIF_ADDR32) ? IA32_PAGE_OFFSET : TASK_SIZE_MAX which is the same as TASK_SIZE. Or, do we want a new macro? #define IBT_BITMAP_SIZE (test_thread_flag(TIF_ADDR32) ? \ (IA32_PAGE_OFFSET / PAGE_SIZE / BITS_PER_BYTE) : \ (TASK_SIZE_MAX / PAGE_SIZE / BITS_PER_BYTE)) Yu-cheng From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by kanga.kvack.org (Postfix) with ESMTP id 3EAEF6B000A for ; Fri, 5 Oct 2018 13:03:11 -0400 (EDT) Received: by mail-pl1-f198.google.com with SMTP id w18-v6so11559196plp.3 for ; Fri, 05 Oct 2018 10:03:11 -0700 (PDT) Received: from mga05.intel.com (mga05.intel.com. [192.55.52.43]) by mx.google.com with ESMTPS id h25-v6si9149121pgn.567.2018.10.05.10.03.09 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 10:03:09 -0700 (PDT) Message-ID: Subject: Re: [RFC PATCH v4 3/9] x86/cet/ibt: Add IBT legacy code bitmap allocation function From: Yu-cheng Yu Date: Fri, 05 Oct 2018 09:58:24 -0700 In-Reply-To: <5BF3AE8F-CC2A-4160-9FF6-FEA171A76371@amacapital.net> References: <20180921150553.21016-1-yu-cheng.yu@intel.com> <20180921150553.21016-4-yu-cheng.yu@intel.com> <20181003195702.GF32759@asgard.redhat.com> <5BF3AE8F-CC2A-4160-9FF6-FEA171A76371@amacapital.net> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: owner-linux-mm@kvack.org List-ID: To: Andy Lutomirski Cc: Eugene Syromiatnikov , x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue On Fri, 2018-10-05 at 09:28 -0700, Andy Lutomirski wrote: > > On Oct 5, 2018, at 9:13 AM, Yu-cheng Yu wrote: > > > > > On Wed, 2018-10-03 at 21:57 +0200, Eugene Syromiatnikov wrote: > > > > On Fri, Sep 21, 2018 at 08:05:47AM -0700, Yu-cheng Yu wrote: > > > > Indirect branch tracking provides an optional legacy code bitmap > > > > that indicates locations of non-IBT compatible code. When set, > > > > each bit in the bitmap represents a page in the linear address is > > > > legacy code. > > > > > > > > We allocate the bitmap only when the application requests it. > > > > Most applications do not need the bitmap. > > > > > > > > Signed-off-by: Yu-cheng Yu > > > > --- > > > > arch/x86/kernel/cet.c | 45 +++++++++++++++++++++++++++++++++++++++++++ > > > > 1 file changed, 45 insertions(+) > > > > > > > > diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c > > > > index 6adfe795d692..a65d9745af08 100644 > > > > --- a/arch/x86/kernel/cet.c > > > > +++ b/arch/x86/kernel/cet.c > > > > @@ -314,3 +314,48 @@ void cet_disable_ibt(void) > > > > wrmsrl(MSR_IA32_U_CET, r); > > > > current->thread.cet.ibt_enabled = 0; > > > > } > > > > + > > > > +int cet_setup_ibt_bitmap(void) > > > > +{ > > > > + u64 r; > > > > + unsigned long bitmap; > > > > + unsigned long size; > > > > + > > > > + if (!cpu_feature_enabled(X86_FEATURE_IBT)) > > > > + return -EOPNOTSUPP; > > > > + > > > > + if (!current->thread.cet.ibt_bitmap_addr) { > > > > + /* > > > > + * Calculate size and put in thread header. > > > > + * may_expand_vm() needs this information. > > > > + */ > > > > + size = TASK_SIZE / PAGE_SIZE / BITS_PER_BYTE; > > > > > > TASK_SIZE_MAX is likely needed here, as an application can easily switch > > > between long an 32-bit protected mode. And then the case of a CPU that > > > doesn't support 5LPT. > > > > If we had calculated bitmap size from TASK_SIZE_MAX, all 32-bit apps would > > have > > failed the allocation for bitmap size > TASK_SIZE. Please see values below, > > which is printed from the current code. > > > > Yu-cheng > > > > > > x64: > > TASK_SIZE_MAX = 0000 7fff ffff f000 > > TASK_SIZE = 0000 7fff ffff f000 > > bitmap size = 0000 0000 ffff ffff > > > > x32: > > TASK_SIZE_MAX = 0000 7fff ffff f000 > > TASK_SIZE = 0000 0000 ffff e000 > > bitmap size = 0000 0000 0001 ffff > > > > I havena??t followed all the details here, but I have a general policy of > objecting to any new use of TASK_SIZE. If you really really need to depend on > 32-bitness in new code, please figure out what exactly you mean by a??32-bita?? > and use an explicit check. The explicit check would be: test_thread_flag(TIF_ADDR32) ? IA32_PAGE_OFFSET : TASK_SIZE_MAX which is the same as TASK_SIZE. Or, do we want a new macro? #define IBT_BITMAP_SIZE (test_thread_flag(TIF_ADDR32) ? \ (IA32_PAGE_OFFSET / PAGE_SIZE / BITS_PER_BYTE) : \ (TASK_SIZE_MAX / PAGE_SIZE / BITS_PER_BYTE)) Yu-cheng