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From: "Verma, Vishal L" <vishal.l.verma@intel.com>
To: "linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
	"linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>
Cc: "Williams, Dan J" <dan.j.williams@intel.com>,
	"Widawsky, Ben" <ben.widawsky@intel.com>,
	"Douglas, Chet R" <chet.r.douglas@intel.com>
Subject: Re: ACPI Working Group Code First ECR for a new CXL Root Object
Date: Fri, 15 Jan 2021 03:17:52 +0000	[thread overview]
Message-ID: <ab06ae5c27a222ec261195e291ecadf655aedeb2.camel@intel.com> (raw)
In-Reply-To: <ecfd911dc8b9a5bac89d1de68047400d15525232.camel@intel.com>

On Thu, 2020-12-03 at 20:12 +0000, Verma, Vishal L wrote:
> This is a public RFC of an ACPI proposal to add a new CXL Root Object
> that indicates the presence of a CXL hierarchy. The proposal is being
> made in the new 'Code First' workflow of the ACPI Spec Working Group.
> The subject matter here has been explored in previously posted patches
> to QEMU[1] as well as Linux[2]. These patches have served as a proof-of-
> concept test vehicle to help ensure that the proposal works in practice.
> The cover letter in series [2] goes into additional detail (section
> titled 'ACPI0017') for the reasoning behind the proposal, and what is
> needed beyond what's described in the CXL 2.0 spec.
> 
> The change proposal that follows is in markdown format.
> 
> [1]: https://lore.kernel.org/qemu-devel/20201111054724.794888-1-ben.widawsky@intel.com/
> [2]: https://lore.kernel.org/linux-cxl/20201111054356.793390-1-ben.widawsky@intel.com/
> 
> ----
> 
> # Title: Add CXL Root Object _HID
> 
> # Status: Draft

This ECR was approved in the ASWG today without any modifications, and
this content can be expected to be present in the next release of the
specification.

> 
> # Document: ACPI Specification 6.4
> 
> # License
> SPDX-License Identifier: CC-BY-4.0
> 
> # Submitter:
> * Sponsor: Vishal Verma, Intel
> * Creators/Contributors:
>     * Chet Douglas, Intel
>     * Ben Widawsky, Intel
>     * Dan Williams, Intel
>     * Vishal Verma, Intel
> 
> # Summary of the Change
> Add “Compute Express Link Root Object” enumeration value to the ACPI
> Device IDs Table (5.160).
> 
> # Benefits of the Change
> Compute Express Link (CXL) is a new high-speed CPU-to-Device and CPU-to-
> Memory interconnect. The new ACPI Device ID represents a singleton
> device that allows the OSPM to trigger the enumeration of the CXL.mem
> address space, and indicates the presence of cross Host Bridge
> (ACPI0016) interleaved CXL.mem resources.
> 
> # Impact of the Change
> One new row added to the ACPI Device IDs table (5.160).
> 
> # References
> * Compute Express Link Specification v2.0,
> <https://www.computeexpresslink.org/>
> 
> # Detailed Description of the Change
> 
> Add “Compute Express Link Root Object” enumeration device
> 
> ### 5.6.7 Device Class-Specific Objects
> 
> Most device objects are controlled through generic objects and  ...
> 
> Table 5.160 ACPI Device IDs
> 
> > Value | Description |
> > :--- | :---: | :---: | :--------------------------- |
> > .. | .. |
> > ACPI0017 | **Compute Express Link Root Object:** This device
> represents the root of a CXL capable device hierarchy. It shall be
> present whenever the platform allows OSPM to dynamically assign CXL
> endpoints to a platform address space. |
> 
> ## Special Instructions


  reply	other threads:[~2021-01-15  3:19 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-03 20:12 ACPI Working Group Code First ECR for a new CXL Root Object Verma, Vishal L
2021-01-15  3:17 ` Verma, Vishal L [this message]
2021-01-15  3:49   ` Ben Widawsky

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