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([2602:ae:1544:6601:226e:47e1:b8cd:a957]) by smtp.gmail.com with ESMTPSA id u14-20020a62ed0e000000b005ac419804d3sm12125400pfh.186.2023.03.23.09.07.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Mar 2023 09:07:12 -0700 (PDT) Message-ID: Date: Thu, 23 Mar 2023 09:07:10 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx Content-Language: en-US To: "Wu, Fei" , LIU Zhiwei , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Christoph Muellner References: <20230323024412.324085-1-fei2.wu@intel.com> <20230323024412.324085-2-fei2.wu@intel.com> <9423db2e-257f-016d-b404-17d8e5adc0ac@linux.alibaba.com> <7db6d615-5ddc-5e1b-1d3c-a85c22e6af74@intel.com> From: Richard Henderson In-Reply-To: <7db6d615-5ddc-5e1b-1d3c-a85c22e6af74@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/22/23 23:00, Wu, Fei wrote: >>> +    ctx->priv = env->priv; >> >> This is not right. You should put env->priv into tb flags before you use >> it in translation. >> > I see some other env usages in this function, when will env->priv and > tb_flags.priv mismatch (assume we have recorded priv in tb_flags)? You are correct that they should match, because of tb_flags, but it is bad form to read from env, as that leads to errors. Since you *can* read the same data from tb_flags, you should. The read of misa_ext and misa_mxl_max are correct, because they are constant set at cpu init/realize. The read of vstart is incorrect. The TB_FLAGS field is VL_EQ_VLMAX, which includes a test for vstart == 0, but the smaller vstart == 0 test is not extractable from that. Thus the usage in e.g. vext_check_reduction is incorrect. One would require a new TB_FLAGS bit to encode vstart ==/!= 0 alone. r~