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[108.49.102.102]) by smtp.gmail.com with ESMTPSA id w4sm5226471qtc.5.2020.07.15.15.32.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 15:32:35 -0700 (PDT) Message-ID: Subject: Re: [PATCH 0/8] drm/mgag200: Support desktop chips From: Lyude Paul To: Thomas Zimmermann , daniel@ffwll.ch, airlied@redhat.com, sam@ravnborg.org, emil.velikov@collabora.com, krzk@kernel.org, john.p.donnelly@Oracle.com, rong.a.chen@intel.com, kraxel@redhat.com, eich@suse.com, tiwai@suse.de Date: Wed, 15 Jul 2020 18:32:34 -0400 In-Reply-To: <20200715145902.13122-1-tzimmermann@suse.de> References: <20200715145902.13122-1-tzimmermann@suse.de> Organization: Red Hat User-Agent: Evolution 3.36.3 (3.36.3-1.fc32) MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: lyude@redhat.com Cc: dri-devel@lists.freedesktop.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Will try to look over this tomorrow, jfyi On Wed, 2020-07-15 at 16:58 +0200, Thomas Zimmermann wrote: > This patchset puts device initialization in the correct order and > adds support for G200 Desktop chips (PCI ids 0x520 and 0x521). > > The first 7 patches prepare the driver. Desktop chips would probably > work without them, but since we're at it we can also do it right. > > Patch 1 enables cached page mappings GEM buffers. SHMEM supports > this well now and the MGA device does not access the buffer memory > directly. So now corrupt display output is to be expected. > > Patches 2 to 6 fix the initialization of device registers. Several > fundamental registers were only done late during device initialization. > This was probably not a problem in practice, as the VGA BIOS does the > setup iduring POST anyway. These patches move the code to the beginning > of the device initialization. If we ever have to POST a MGA device from > the driver, the corect order of operations counts. > > G200SEs store a unique id in the device structure. Patch 7 moves the > value to model-specific data area. This will be helpful for patch 8. > > Patch 8 adds support for desktop chips' PCI ids. all the memory and > modesetting code continues to work as before. The PLL setup code gets > an additional helper for the new HW. PCI and DAC regsiters get a few > new default values. Most significantly, the driver parses the VGA BIOS > for clock settings. It's all separate from the server code, so no > regressions are to be expected. > > The new HW support is based on an earlier patch the was posted in July > 2017. [1] > > Tested on G200EW and G200 AGP hardware by running the fbdev console, > Weston and Gnome on Xorg. > > [1] https://lists.freedesktop.org/archives/dri-devel/2017-July/147647.html > > Thomas Zimmermann (8): > drm/mgag200: Enable caching for SHMEM pages > drm/mgag200: Move register initialization into helper function > drm/mgag200: Initialize PCI registers early during device setup > drm/mgag200: Enable MGA mode during device register initialization > drm/mgag200: Set MISC memory flags in mm init code > drm/mgag200: Clear field during MM init > drm/mgag200: Move G200SE's unique id into model-specific data > drm/mgag200: Add support for G200 desktop cards > > MAINTAINERS | 2 +- > drivers/gpu/drm/mgag200/Kconfig | 12 +- > drivers/gpu/drm/mgag200/mgag200_drv.c | 213 +++++++++++++++++++++++-- > drivers/gpu/drm/mgag200/mgag200_drv.h | 19 ++- > drivers/gpu/drm/mgag200/mgag200_mm.c | 8 + > drivers/gpu/drm/mgag200/mgag200_mode.c | 153 +++++++++++------- > drivers/gpu/drm/mgag200/mgag200_reg.h | 4 + > 7 files changed, 328 insertions(+), 83 deletions(-) > > -- > 2.27.0 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel