Re: [PATCH 1/6] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP

From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>, qemu-devel@nongnu.org
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
	Huacai Chen <chenhuacai@kernel.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [PATCH 1/6] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP
Date: Wed, 13 Jan 2021 10:04:51 +0800	[thread overview]
Message-ID: <ad19c6f5-d97f-71a3-d5ad-1ed4d4879683@flygoat.com> (raw)
In-Reply-To: <20210112215504.2093955-2-f4bug@amsat.org>

在 2021/1/13 上午5:54, Philippe Mathieu-Daudé 写道:
> There is no issue having multiple enum declarations with
> the same value. As we are going to remove the OPC_MULT_G_2E
> definition in few commits, restore the OPC_ADDUH_QB_DSP and
> OPC_MUL_PH_DSP definitions and use them where they belong.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

> ---
>   target/mips/translate.c | 18 +++++-------------
>   1 file changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index a2b3026132d..cbd152eff50 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -399,16 +399,14 @@ enum {
>       OPC_ADDU_OB_DSP    = 0x14 | OPC_SPECIAL3,
>       OPC_ABSQ_S_PH_DSP  = 0x12 | OPC_SPECIAL3,
>       OPC_ABSQ_S_QH_DSP  = 0x16 | OPC_SPECIAL3,
> -    /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E.  */
> -    /* OPC_ADDUH_QB_DSP   = 0x18 | OPC_SPECIAL3,  */
> +    OPC_ADDUH_QB_DSP   = 0x18 | OPC_SPECIAL3,
>       OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
>       OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3,
>       /* MIPS DSP GPR-Based Shift Sub-class */
>       OPC_SHLL_QB_DSP    = 0x13 | OPC_SPECIAL3,
>       OPC_SHLL_OB_DSP    = 0x17 | OPC_SPECIAL3,
>       /* MIPS DSP Multiply Sub-class insns */
> -    /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP.  */
> -    /* OPC_MUL_PH_DSP     = 0x18 | OPC_SPECIAL3,  */
> +    OPC_MUL_PH_DSP     = 0x18 | OPC_SPECIAL3,
>       OPC_DPA_W_PH_DSP   = 0x30 | OPC_SPECIAL3,
>       OPC_DPAQ_W_QH_DSP  = 0x34 | OPC_SPECIAL3,
>       /* DSP Bit/Manipulation Sub-class */
> @@ -566,7 +564,6 @@ enum {
>       OPC_MULQ_S_PH      = (0x1E << 6) | OPC_ADDU_QB_DSP,
>   };
>   
> -#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
>   #define MASK_ADDUH_QB(op)           (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
>   enum {
>       /* MIPS DSP Arithmetic Sub-class */
> @@ -22681,8 +22678,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
>       gen_load_gpr(v2_t, v2);
>   
>       switch (op1) {
> -    /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
> -    case OPC_MULT_G_2E:
> +    case OPC_ADDUH_QB_DSP:
>           check_dsp_r2(ctx);
>           switch (op2) {
>           case OPC_ADDUH_QB:
> @@ -23376,11 +23372,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
>       gen_load_gpr(v2_t, v2);
>   
>       switch (op1) {
> -    /*
> -     * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
> -     * the same mask and op1.
> -     */
> -    case OPC_MULT_G_2E:
> +    case OPC_MUL_PH_DSP:
>           check_dsp_r2(ctx);
>           switch (op2) {
>           case  OPC_MUL_PH:
> @@ -27337,7 +27329,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
>            * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
>            * the same mask and op1.
>            */
> -        if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) {
> +        if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) {
>               op2 = MASK_ADDUH_QB(ctx->opcode);
>               switch (op2) {
>               case OPC_ADDUH_QB: