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* [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR
@ 2020-04-10 18:55 Marek Vasut
  2020-04-10 18:55 ` [PATCH V2 2/6] ARM: stm32: Add board_early_init_f() to SPL Marek Vasut
                   ` (5 more replies)
  0 siblings, 6 replies; 14+ messages in thread
From: Marek Vasut @ 2020-04-10 18:55 UTC (permalink / raw)
  To: u-boot

Add default U-Boot configuration for the DHCOR SoM on AV96 board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
---
V2: No change
---
 configs/stm32mp15_dhcor_basic_defconfig | 138 ++++++++++++++++++++++++
 1 file changed, 138 insertions(+)
 create mode 100644 configs/stm32mp15_dhcor_basic_defconfig

diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
new file mode 100644
index 0000000000..4a968609fe
--- /dev/null
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -0,0 +1,138 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_TARGET_DH_STM32MP1_PDK2=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_SPL_TEXT_BASE=0x2FFC2500
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SYS_PROMPT="STM32MP> "
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcor-avenger96"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=10000000
+CONFIG_USE_ENV_SPI_MODE=y
+CONFIG_ENV_SPI_MODE=0x0
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=1536
+CONFIG_STM32_ADC=y
+CONFIG_SPL_BLOCK_CACHE=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_VIRT=y
+CONFIG_DM_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_STM32=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_STM32_IPCC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_STM32_SDMMC2=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_SPL_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_KS8851_MLL=y
+CONFIG_PHY=y
+CONFIG_PHY_STM32_USBPHYC=y
+CONFIG_PINCONF=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_PINCTRL_STMFX=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_PMIC_STPMIC1=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_STM32_VREFBUF=y
+CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_REMOTEPROC_STM32_COPRO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_STM32=y
+CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_STM32_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="dh"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0483
+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_DSI=y
+CONFIG_VIDEO_STM32_MAX_XRES=1280
+CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_LZO=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH V2 2/6] ARM: stm32: Add board_early_init_f() to SPL
  2020-04-10 18:55 [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR Marek Vasut
@ 2020-04-10 18:55 ` Marek Vasut
  2020-04-22  8:26   ` Patrick DELAUNAY
  2020-04-10 18:55 ` [PATCH V2 3/6] ARM: stm32: Implement board coding on AV96 Marek Vasut
                   ` (4 subsequent siblings)
  5 siblings, 1 reply; 14+ messages in thread
From: Marek Vasut @ 2020-04-10 18:55 UTC (permalink / raw)
  To: u-boot

Add weak implementation of board_early_init_f() hook into the
STM32MP1 SPL. This can be used to read out e.g. configuration
straps before initializing the DRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
---
V2: No change
---
 arch/arm/mach-stm32mp/spl.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index ca4231cd0d..cd14d1065e 100644
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -76,6 +76,11 @@ void spl_display_print(void)
 }
 #endif
 
+__weak int board_early_init_f(void)
+{
+	return 0;
+}
+
 void board_init_f(ulong dummy)
 {
 	struct udevice *dev;
@@ -110,6 +115,12 @@ void board_init_f(ulong dummy)
 	/* enable console uart printing */
 	preloader_console_init();
 
+	ret = board_early_init_f();
+	if (ret) {
+		debug("board_early_init_f() failed: %d\n", ret);
+		hang();
+	}
+
 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 	if (ret) {
 		printf("DRAM init failed: %d\n", ret);
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH V2 3/6] ARM: stm32: Implement board coding on AV96
  2020-04-10 18:55 [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR Marek Vasut
  2020-04-10 18:55 ` [PATCH V2 2/6] ARM: stm32: Add board_early_init_f() to SPL Marek Vasut
@ 2020-04-10 18:55 ` Marek Vasut
  2020-04-22  8:36   ` Patrick DELAUNAY
  2020-04-10 18:55 ` [PATCH V2 4/6] ram: stm32mp1: Add support for multiple configs Marek Vasut
                   ` (3 subsequent siblings)
  5 siblings, 1 reply; 14+ messages in thread
From: Marek Vasut @ 2020-04-10 18:55 UTC (permalink / raw)
  To: u-boot

The AV96 board does exist in multiple variants. To cater for all of
them, implement board code handling. There are two GPIOs which code
the type of the board, read them out and use the value to pick the
correct device tree from an fitImage.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
---
V2: No change
---
 arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi    |  3 +
 .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi   |  1 +
 arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi    |  9 +++
 board/dhelectronics/dh_stm32mp1/Kconfig       |  2 +-
 board/dhelectronics/dh_stm32mp1/board.c       | 61 +++++++++++++++++++
 .../dh_stm32mp1/u-boot-dhcom.its              | 39 ++++++++++++
 .../dh_stm32mp1/u-boot-dhcor.its              | 39 ++++++++++++
 configs/stm32mp15_dhcom_basic_defconfig       |  3 +
 configs/stm32mp15_dhcor_basic_defconfig       |  3 +
 include/configs/dh_stm32mp1.h                 | 15 +++++
 10 files changed, 174 insertions(+), 1 deletion(-)
 create mode 100644 board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
 create mode 100644 board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
 create mode 100644 include/configs/dh_stm32mp1.h

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index eba3588540..fcdc5e6859 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -19,10 +19,13 @@
 	};
 
 	config {
+		u-boot,dm-pre-reloc;
 		u-boot,boot-led = "heartbeat";
 		u-boot,error-led = "error";
 		st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
 		st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+		#gpio-cells = <2>;
+		dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
 	};
 
 	led {
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
index 4207a96618..7ccec95f15 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
@@ -15,6 +15,7 @@
 	config {
 		u-boot,boot-led = "led1";
 		u-boot,error-led = "led4";
+		dh,board-coding-gpios = <&gpiog 13 0>, <&gpiod 9 0>;
 	};
 };
 
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index 02dad81b0b..17a23ae21c 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -11,6 +11,15 @@
 #include "stm32mp157-u-boot.dtsi"
 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
 
+/ {
+	u-boot,dm-pre-reloc;
+	config {
+		u-boot,dm-pre-reloc;
+		#gpio-cells = <2>;
+		dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
+	};
+};
+
 &i2c4 {
 	u-boot,dm-pre-reloc;
 };
diff --git a/board/dhelectronics/dh_stm32mp1/Kconfig b/board/dhelectronics/dh_stm32mp1/Kconfig
index 8eab986640..0a839f2546 100644
--- a/board/dhelectronics/dh_stm32mp1/Kconfig
+++ b/board/dhelectronics/dh_stm32mp1/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
 	default "dhelectronics"
 
 config SYS_CONFIG_NAME
-	default "stm32mp1"
+	default "dh_stm32mp1"
 
 config ENV_SECT_SIZE
 	default 0x10000 if ENV_IS_IN_SPI_FLASH
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index a3458a2623..b72d113a6f 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -133,6 +133,62 @@ int checkboard(void)
 	return 0;
 }
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+static u8 brdcode __section("data");
+static u8 somcode __section("data");
+
+static void board_get_coding_straps(void)
+{
+	struct gpio_desc gpio[4];
+	ofnode node;
+	int i, ret;
+
+	node = ofnode_path("/config");
+	if (!ofnode_valid(node)) {
+		printf("%s: no /config node?\n", __func__);
+		return;
+	}
+
+	brdcode = 0;
+	somcode = 0;
+
+	ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
+					      gpio, ARRAY_SIZE(gpio),
+					      GPIOD_IS_IN);
+	for (i = 0; i < ret; i++)
+		somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
+	ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
+					      gpio, ARRAY_SIZE(gpio),
+					      GPIOD_IS_IN);
+	for (i = 0; i < ret; i++)
+		brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
+	printf("Code:  SoM:rev=%d Board:rev=%d\n", somcode, brdcode);
+}
+
+int board_early_init_f(void)
+{
+	board_get_coding_straps();
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	char test[20];
+
+	snprintf(test, sizeof(test), "somrev%d_boardrev%d", somcode, brdcode);
+
+	if (!strcmp(name, test))
+		return 0;
+
+	return -EINVAL;
+}
+#endif
+#endif
+
 static void board_key_check(void)
 {
 #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
@@ -478,6 +534,11 @@ int board_late_init(void)
 	if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
 		env_set("bootdelay", "0");
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+	env_set_ulong("dh_som_rev", somcode);
+	env_set_ulong("dh_board_rev", brdcode);
+#endif
+
 	return 0;
 }
 
diff --git a/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its b/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
new file mode 100644
index 0000000000..a4574ea135
--- /dev/null
+++ b/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
@@ -0,0 +1,39 @@
+/dts-v1/;
+
+/ {
+	description = "U-Boot mainline";
+	#address-cells = <1>;
+
+	images {
+		uboot {
+			description = "U-Boot (32-bit)";
+			data = /incbin/("../../../u-boot-nodtb.bin");
+			type = "standalone";
+			os = "U-Boot";
+			arch = "arm";
+			compression = "none";
+			load = <0xc0100000>;
+			entry = <0xc0100000>;
+		};
+
+		fdt-1 {
+			description = ".dtb";
+			data = /incbin/("../../../arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "config-1";
+
+		config-1 {
+			description = "somrev0_boardrev0"; /* SoM+board model */
+			loadables = "uboot";
+			fdt = "fdt-1";
+		};
+
+		/* Add 587-100..587-400 with fdt-2..fdt-4 here */
+	};
+};
diff --git a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its b/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
new file mode 100644
index 0000000000..0a8b6ac857
--- /dev/null
+++ b/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
@@ -0,0 +1,39 @@
+/dts-v1/;
+
+/ {
+	description = "U-Boot mainline";
+	#address-cells = <1>;
+
+	images {
+		uboot {
+			description = "U-Boot (32-bit)";
+			data = /incbin/("../../../u-boot-nodtb.bin");
+			type = "standalone";
+			os = "U-Boot";
+			arch = "arm";
+			compression = "none";
+			load = <0xc0100000>;
+			entry = <0xc0100000>;
+		};
+
+		fdt-1 {
+			description = ".dtb";
+			data = /incbin/("../../../arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "config-1";
+
+		config-1 {
+			description = "somrev0_boardrev1"; /* SoM+board model */
+			loadables = "uboot";
+			fdt = "fdt-1";
+		};
+
+		/* Add 586-200..586-400 with fdt-2..fdt-4 here */
+	};
+};
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index 28824cf813..81222ce444 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -11,7 +11,10 @@ CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its"
 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
 CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index 4a968609fe..e75ed1a932 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -11,7 +11,10 @@ CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its"
 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
 CONFIG_SPL_I2C_SUPPORT=y
diff --git a/include/configs/dh_stm32mp1.h b/include/configs/dh_stm32mp1.h
new file mode 100644
index 0000000000..89d317ba2b
--- /dev/null
+++ b/include/configs/dh_stm32mp1.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2020 Marek Vasut <marex@denx.de>
+ *
+ * Configuration settings for the DH STM32MP15x SoMs
+ */
+
+#ifndef __CONFIG_DH_STM32MP1_H__
+#define __CONFIG_DH_STM32MP1_H__
+
+#include <configs/stm32mp1.h>
+
+#define CONFIG_SPL_TARGET		"u-boot.itb"
+
+#endif
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH V2 4/6] ram: stm32mp1: Add support for multiple configs
  2020-04-10 18:55 [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR Marek Vasut
  2020-04-10 18:55 ` [PATCH V2 2/6] ARM: stm32: Add board_early_init_f() to SPL Marek Vasut
  2020-04-10 18:55 ` [PATCH V2 3/6] ARM: stm32: Implement board coding on AV96 Marek Vasut
@ 2020-04-10 18:55 ` Marek Vasut
  2020-04-21 17:57   ` Patrick DELAUNAY
  2020-04-10 18:55 ` [PATCH V2 5/6] ARM: dts: stm32: Rework DDR DT inclusion Marek Vasut
                   ` (2 subsequent siblings)
  5 siblings, 1 reply; 14+ messages in thread
From: Marek Vasut @ 2020-04-10 18:55 UTC (permalink / raw)
  To: u-boot

Add support for multiple DRAM configuration subnodes, while retaining
the support for a single flat DRAM configuration node. This is useful
on systems which can be manufactured in multiple configurations and
where the DRAM configuration can be determined at runtime.

The code is augmented by a function which can be overridden on board
level, allowing a match on the configuration node name, very much like
the fitImage configuration node name matching works. The default match
is on the single top-level DRAM configuration, if matching on subnodes
is required, then this board_stm32mp1_ddr_config_name_match() must be
overridden.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
---
V2: Match on compatible string
---
 drivers/ram/stm32mp1/stm32mp1_ram.c | 39 +++++++++++++++++++++++++----
 1 file changed, 34 insertions(+), 5 deletions(-)

diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c
index eb78f1198d..21c220694e 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ram.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -57,6 +57,33 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
 	return 0;
 }
 
+__weak int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
+						const char *name)
+{
+	return 0;	/* Always match */
+}
+
+static ofnode stm32mp1_ddr_get_ofnode(struct udevice *dev)
+{
+	const char *name;
+	int name_size;
+	ofnode node;
+
+	node = dev_ofnode(dev);
+	name = ofnode_get_property(node, "compatible", &name_size);
+	if (!board_stm32mp1_ddr_config_name_match(dev, name))
+		return node;
+
+	dev_for_each_subnode(node, dev) {
+		name = ofnode_get_property(node, "compatible", &name_size);
+
+		if (!board_stm32mp1_ddr_config_name_match(dev, name))
+			return node;
+	}
+
+	return ofnode_null();
+}
+
 static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
 {
 	struct ddr_info *priv = dev_get_priv(dev);
@@ -64,6 +91,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
 	unsigned int idx;
 	struct clk axidcg;
 	struct stm32mp1_ddr_config config;
+	ofnode node = stm32mp1_ddr_get_ofnode(dev);
 
 #define PARAM(x, y) \
 	{ x,\
@@ -87,9 +115,9 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
 		PHY_PARAM(cal)
 	};
 
-	config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
-	config.info.size = dev_read_u32_default(dev, "st,mem-size", 0);
-	config.info.name = dev_read_string(dev, "st,mem-name");
+	config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0);
+	config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
+	config.info.name = ofnode_read_string(node, "st,mem-name");
 	if (!config.info.name) {
 		debug("%s: no st,mem-name\n", __func__);
 		return -EINVAL;
@@ -97,7 +125,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
 	printf("RAM: %s\n", config.info.name);
 
 	for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
-		ret = dev_read_u32_array(dev, param[idx].name,
+		ret = ofnode_read_u32_array(node, param[idx].name,
 					 (void *)((u32)&config +
 						  param[idx].offset),
 					 param[idx].size);
@@ -164,7 +192,8 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
 	priv->info.size = 0;
 	return stm32mp1_ddr_setup(dev);
 #else
-	priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
+	ofnode node = stm32mp1_ddr_get_ofnode(dev);
+	priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
 	return 0;
 #endif
 }
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH V2 5/6] ARM: dts: stm32: Rework DDR DT inclusion
  2020-04-10 18:55 [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR Marek Vasut
                   ` (2 preceding siblings ...)
  2020-04-10 18:55 ` [PATCH V2 4/6] ram: stm32mp1: Add support for multiple configs Marek Vasut
@ 2020-04-10 18:55 ` Marek Vasut
  2020-04-22  9:06   ` Patrick DELAUNAY
  2020-04-10 18:55 ` [PATCH V2 6/6] ARM: stm32: Implement DDR3 coding on DHCOR SoM Marek Vasut
  2020-04-22  8:24 ` [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR Patrick DELAUNAY
  5 siblings, 1 reply; 14+ messages in thread
From: Marek Vasut @ 2020-04-10 18:55 UTC (permalink / raw)
  To: u-boot

Adjust the DDR configuration dtsi such that they only generate the
DRAM configuration node, the DDR controller node is moved into the
stm32mp157-u-boot.dtsi itself. This permits including multiple DDR
configuration dtsi files in board DT.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
---
V2: Add compatible string
---
 arch/arm/dts/stm32mp15-ddr.dtsi               | 358 +++++++++++-------
 .../dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi   |   1 +
 .../dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi   |   1 +
 arch/arm/dts/stm32mp157-u-boot.dtsi           |  25 ++
 4 files changed, 248 insertions(+), 137 deletions(-)

diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
index 38f29bb789..026237b088 100644
--- a/arch/arm/dts/stm32mp15-ddr.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr.dtsi
@@ -2,153 +2,237 @@
 /*
  * Copyright : STMicroelectronics 2018
  */
+#include <linux/stringify.h>
 
-/ {
-	soc {
-		ddr: ddr at 5a003000 {
-			u-boot,dm-pre-reloc;
+&ddr {
+	config-DDR_MEM_COMPATIBLE {
+		u-boot,dm-pre-reloc;
 
-			compatible = "st,stm32mp1-ddr";
+		compatible = __stringify(st,DDR_MEM_COMPATIBLE);
 
-			reg = <0x5A003000 0x550
-			       0x5A004000 0x234>;
+		st,mem-name = DDR_MEM_NAME;
+		st,mem-speed = <DDR_MEM_SPEED>;
+		st,mem-size = <DDR_MEM_SIZE>;
 
-			clocks = <&rcc AXIDCG>,
-				 <&rcc DDRC1>,
-				 <&rcc DDRC2>,
-				 <&rcc DDRPHYC>,
-				 <&rcc DDRCAPB>,
-				 <&rcc DDRPHYCAPB>;
+		st,ctl-reg = <
+			DDR_MSTR
+			DDR_MRCTRL0
+			DDR_MRCTRL1
+			DDR_DERATEEN
+			DDR_DERATEINT
+			DDR_PWRCTL
+			DDR_PWRTMG
+			DDR_HWLPCTL
+			DDR_RFSHCTL0
+			DDR_RFSHCTL3
+			DDR_CRCPARCTL0
+			DDR_ZQCTL0
+			DDR_DFITMG0
+			DDR_DFITMG1
+			DDR_DFILPCFG0
+			DDR_DFIUPD0
+			DDR_DFIUPD1
+			DDR_DFIUPD2
+			DDR_DFIPHYMSTR
+			DDR_ODTMAP
+			DDR_DBG0
+			DDR_DBG1
+			DDR_DBGCMD
+			DDR_POISONCFG
+			DDR_PCCFG
+		>;
 
-			clock-names = "axidcg",
-				      "ddrc1",
-				      "ddrc2",
-				      "ddrphyc",
-				      "ddrcapb",
-				      "ddrphycapb";
+		st,ctl-timing = <
+			DDR_RFSHTMG
+			DDR_DRAMTMG0
+			DDR_DRAMTMG1
+			DDR_DRAMTMG2
+			DDR_DRAMTMG3
+			DDR_DRAMTMG4
+			DDR_DRAMTMG5
+			DDR_DRAMTMG6
+			DDR_DRAMTMG7
+			DDR_DRAMTMG8
+			DDR_DRAMTMG14
+			DDR_ODTCFG
+		>;
 
-			st,mem-name = DDR_MEM_NAME;
-			st,mem-speed = <DDR_MEM_SPEED>;
-			st,mem-size = <DDR_MEM_SIZE>;
+		st,ctl-map = <
+			DDR_ADDRMAP1
+			DDR_ADDRMAP2
+			DDR_ADDRMAP3
+			DDR_ADDRMAP4
+			DDR_ADDRMAP5
+			DDR_ADDRMAP6
+			DDR_ADDRMAP9
+			DDR_ADDRMAP10
+			DDR_ADDRMAP11
+		>;
 
-			st,ctl-reg = <
-				DDR_MSTR
-				DDR_MRCTRL0
-				DDR_MRCTRL1
-				DDR_DERATEEN
-				DDR_DERATEINT
-				DDR_PWRCTL
-				DDR_PWRTMG
-				DDR_HWLPCTL
-				DDR_RFSHCTL0
-				DDR_RFSHCTL3
-				DDR_CRCPARCTL0
-				DDR_ZQCTL0
-				DDR_DFITMG0
-				DDR_DFITMG1
-				DDR_DFILPCFG0
-				DDR_DFIUPD0
-				DDR_DFIUPD1
-				DDR_DFIUPD2
-				DDR_DFIPHYMSTR
-				DDR_ODTMAP
-				DDR_DBG0
-				DDR_DBG1
-				DDR_DBGCMD
-				DDR_POISONCFG
-				DDR_PCCFG
-			>;
+		st,ctl-perf = <
+			DDR_SCHED
+			DDR_SCHED1
+			DDR_PERFHPR1
+			DDR_PERFLPR1
+			DDR_PERFWR1
+			DDR_PCFGR_0
+			DDR_PCFGW_0
+			DDR_PCFGQOS0_0
+			DDR_PCFGQOS1_0
+			DDR_PCFGWQOS0_0
+			DDR_PCFGWQOS1_0
+			DDR_PCFGR_1
+			DDR_PCFGW_1
+			DDR_PCFGQOS0_1
+			DDR_PCFGQOS1_1
+			DDR_PCFGWQOS0_1
+			DDR_PCFGWQOS1_1
+		>;
 
-			st,ctl-timing = <
-				DDR_RFSHTMG
-				DDR_DRAMTMG0
-				DDR_DRAMTMG1
-				DDR_DRAMTMG2
-				DDR_DRAMTMG3
-				DDR_DRAMTMG4
-				DDR_DRAMTMG5
-				DDR_DRAMTMG6
-				DDR_DRAMTMG7
-				DDR_DRAMTMG8
-				DDR_DRAMTMG14
-				DDR_ODTCFG
-			>;
+		st,phy-reg = <
+			DDR_PGCR
+			DDR_ACIOCR
+			DDR_DXCCR
+			DDR_DSGCR
+			DDR_DCR
+			DDR_ODTCR
+			DDR_ZQ0CR1
+			DDR_DX0GCR
+			DDR_DX1GCR
+			DDR_DX2GCR
+			DDR_DX3GCR
+		>;
 
-			st,ctl-map = <
-				DDR_ADDRMAP1
-				DDR_ADDRMAP2
-				DDR_ADDRMAP3
-				DDR_ADDRMAP4
-				DDR_ADDRMAP5
-				DDR_ADDRMAP6
-				DDR_ADDRMAP9
-				DDR_ADDRMAP10
-				DDR_ADDRMAP11
-			>;
+		st,phy-timing = <
+			DDR_PTR0
+			DDR_PTR1
+			DDR_PTR2
+			DDR_DTPR0
+			DDR_DTPR1
+			DDR_DTPR2
+			DDR_MR0
+			DDR_MR1
+			DDR_MR2
+			DDR_MR3
+		>;
 
-			st,ctl-perf = <
-				DDR_SCHED
-				DDR_SCHED1
-				DDR_PERFHPR1
-				DDR_PERFLPR1
-				DDR_PERFWR1
-				DDR_PCFGR_0
-				DDR_PCFGW_0
-				DDR_PCFGQOS0_0
-				DDR_PCFGQOS1_0
-				DDR_PCFGWQOS0_0
-				DDR_PCFGWQOS1_0
-				DDR_PCFGR_1
-				DDR_PCFGW_1
-				DDR_PCFGQOS0_1
-				DDR_PCFGQOS1_1
-				DDR_PCFGWQOS0_1
-				DDR_PCFGWQOS1_1
-			>;
+		st,phy-cal = <
+			DDR_DX0DLLCR
+			DDR_DX0DQTR
+			DDR_DX0DQSTR
+			DDR_DX1DLLCR
+			DDR_DX1DQTR
+			DDR_DX1DQSTR
+			DDR_DX2DLLCR
+			DDR_DX2DQTR
+			DDR_DX2DQSTR
+			DDR_DX3DLLCR
+			DDR_DX3DQTR
+			DDR_DX3DQSTR
+		>;
 
-			st,phy-reg = <
-				DDR_PGCR
-				DDR_ACIOCR
-				DDR_DXCCR
-				DDR_DSGCR
-				DDR_DCR
-				DDR_ODTCR
-				DDR_ZQ0CR1
-				DDR_DX0GCR
-				DDR_DX1GCR
-				DDR_DX2GCR
-				DDR_DX3GCR
-			>;
-
-			st,phy-timing = <
-				DDR_PTR0
-				DDR_PTR1
-				DDR_PTR2
-				DDR_DTPR0
-				DDR_DTPR1
-				DDR_DTPR2
-				DDR_MR0
-				DDR_MR1
-				DDR_MR2
-				DDR_MR3
-			>;
-
-			st,phy-cal = <
-				DDR_DX0DLLCR
-				DDR_DX0DQTR
-				DDR_DX0DQSTR
-				DDR_DX1DLLCR
-				DDR_DX1DQTR
-				DDR_DX1DQSTR
-				DDR_DX2DLLCR
-				DDR_DX2DQTR
-				DDR_DX2DQSTR
-				DDR_DX3DLLCR
-				DDR_DX3DQTR
-				DDR_DX3DQSTR
-			>;
-
-			status = "okay";
-		};
+		status = "okay";
 	};
 };
+
+#undef DDR_MEM_COMPATIBLE
+#undef DDR_MEM_NAME
+#undef DDR_MEM_SPEED
+#undef DDR_MEM_SIZE
+
+#undef DDR_MSTR
+#undef DDR_MRCTRL0
+#undef DDR_MRCTRL1
+#undef DDR_DERATEEN
+#undef DDR_DERATEINT
+#undef DDR_PWRCTL
+#undef DDR_PWRTMG
+#undef DDR_HWLPCTL
+#undef DDR_RFSHCTL0
+#undef DDR_RFSHCTL3
+#undef DDR_RFSHTMG
+#undef DDR_CRCPARCTL0
+#undef DDR_DRAMTMG0
+#undef DDR_DRAMTMG1
+#undef DDR_DRAMTMG2
+#undef DDR_DRAMTMG3
+#undef DDR_DRAMTMG4
+#undef DDR_DRAMTMG5
+#undef DDR_DRAMTMG6
+#undef DDR_DRAMTMG7
+#undef DDR_DRAMTMG8
+#undef DDR_DRAMTMG14
+#undef DDR_ZQCTL0
+#undef DDR_DFITMG0
+#undef DDR_DFITMG1
+#undef DDR_DFILPCFG0
+#undef DDR_DFIUPD0
+#undef DDR_DFIUPD1
+#undef DDR_DFIUPD2
+#undef DDR_DFIPHYMSTR
+#undef DDR_ADDRMAP1
+#undef DDR_ADDRMAP2
+#undef DDR_ADDRMAP3
+#undef DDR_ADDRMAP4
+#undef DDR_ADDRMAP5
+#undef DDR_ADDRMAP6
+#undef DDR_ADDRMAP9
+#undef DDR_ADDRMAP10
+#undef DDR_ADDRMAP11
+#undef DDR_ODTCFG
+#undef DDR_ODTMAP
+#undef DDR_SCHED
+#undef DDR_SCHED1
+#undef DDR_PERFHPR1
+#undef DDR_PERFLPR1
+#undef DDR_PERFWR1
+#undef DDR_DBG0
+#undef DDR_DBG1
+#undef DDR_DBGCMD
+#undef DDR_POISONCFG
+#undef DDR_PCCFG
+#undef DDR_PCFGR_0
+#undef DDR_PCFGW_0
+#undef DDR_PCFGQOS0_0
+#undef DDR_PCFGQOS1_0
+#undef DDR_PCFGWQOS0_0
+#undef DDR_PCFGWQOS1_0
+#undef DDR_PCFGR_1
+#undef DDR_PCFGW_1
+#undef DDR_PCFGQOS0_1
+#undef DDR_PCFGQOS1_1
+#undef DDR_PCFGWQOS0_1
+#undef DDR_PCFGWQOS1_1
+#undef DDR_PGCR
+#undef DDR_PTR0
+#undef DDR_PTR1
+#undef DDR_PTR2
+#undef DDR_ACIOCR
+#undef DDR_DXCCR
+#undef DDR_DSGCR
+#undef DDR_DCR
+#undef DDR_DTPR0
+#undef DDR_DTPR1
+#undef DDR_DTPR2
+#undef DDR_MR0
+#undef DDR_MR1
+#undef DDR_MR2
+#undef DDR_MR3
+#undef DDR_ODTCR
+#undef DDR_ZQ0CR1
+#undef DDR_DX0GCR
+#undef DDR_DX0DLLCR
+#undef DDR_DX0DQTR
+#undef DDR_DX0DQSTR
+#undef DDR_DX1GCR
+#undef DDR_DX1DLLCR
+#undef DDR_DX1DQTR
+#undef DDR_DX1DQSTR
+#undef DDR_DX2GCR
+#undef DDR_DX2DLLCR
+#undef DDR_DX2DQTR
+#undef DDR_DX2DQSTR
+#undef DDR_DX3GCR
+#undef DDR_DX3DLLCR
+#undef DDR_DX3DQTR
+#undef DDR_DX3DQSTR
diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
index 11e8f2bef6..4e2bd47e86 100644
--- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
@@ -16,6 +16,7 @@
  * address mapping : RBC
  * Tc > + 85C : N
  */
+#define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-1x4gb-533mhz
 #define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
 #define DDR_MEM_SPEED 533000
 #define DDR_MEM_SIZE 0x20000000
diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
index 4b70b60554..f10be58ffb 100644
--- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -16,6 +16,7 @@
  * address mapping : RBC
  * Tc > + 85C : N
  */
+#define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-2x4gb-533mhz
 #define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
 #define DDR_MEM_SPEED 533000
 #define DDR_MEM_SIZE 0x40000000
diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi
index 8f9535a4db..1279589a56 100644
--- a/arch/arm/dts/stm32mp157-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157-u-boot.dtsi
@@ -36,6 +36,31 @@
 
 	soc {
 		u-boot,dm-pre-reloc;
+
+		ddr: ddr at 5a003000 {
+			u-boot,dm-pre-reloc;
+
+			compatible = "st,stm32mp1-ddr";
+
+			reg = <0x5A003000 0x550
+			       0x5A004000 0x234>;
+
+			clocks = <&rcc AXIDCG>,
+				 <&rcc DDRC1>,
+				 <&rcc DDRC2>,
+				 <&rcc DDRPHYC>,
+				 <&rcc DDRCAPB>,
+				 <&rcc DDRPHYCAPB>;
+
+			clock-names = "axidcg",
+				      "ddrc1",
+				      "ddrc2",
+				      "ddrphyc",
+				      "ddrcapb",
+				      "ddrphycapb";
+
+			status = "okay";
+		};
 	};
 };
 
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH V2 6/6] ARM: stm32: Implement DDR3 coding on DHCOR SoM
  2020-04-10 18:55 [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR Marek Vasut
                   ` (3 preceding siblings ...)
  2020-04-10 18:55 ` [PATCH V2 5/6] ARM: dts: stm32: Rework DDR DT inclusion Marek Vasut
@ 2020-04-10 18:55 ` Marek Vasut
  2020-04-22  9:08   ` Patrick DELAUNAY
  2020-04-22  8:24 ` [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR Patrick DELAUNAY
  5 siblings, 1 reply; 14+ messages in thread
From: Marek Vasut @ 2020-04-10 18:55 UTC (permalink / raw)
  To: u-boot

The DHCOR board does exist in multiple variants with different DDR3
DRAM sizes. To cater for all of them, implement DDR3 code handling.
There are two GPIOs which code the DRAM size populated on the SoM,
read them out and use the value to pick the correct DDR3 config.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
---
V2: Match on compatible string
---
 arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi |  2 ++
 arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi |  2 ++
 board/dhelectronics/dh_stm32mp1/board.c    | 26 +++++++++++++++++++++-
 configs/stm32mp15_dhcom_basic_defconfig    |  1 +
 configs/stm32mp15_dhcor_basic_defconfig    |  1 +
 5 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index fcdc5e6859..54416acd5c 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/clock/stm32mp1-clksrc.h>
 #include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
 
 / {
@@ -26,6 +27,7 @@
 		st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
 		#gpio-cells = <2>;
 		dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
+		dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
 	};
 
 	led {
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index 17a23ae21c..6db4ac37e1 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -9,6 +9,7 @@
 
 #include <dt-bindings/clock/stm32mp1-clksrc.h>
 #include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
 
 / {
@@ -16,6 +17,7 @@
 	config {
 		u-boot,dm-pre-reloc;
 		#gpio-cells = <2>;
+		dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
 		dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
 	};
 };
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index b72d113a6f..07a2bab10c 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -135,6 +135,7 @@ int checkboard(void)
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 static u8 brdcode __section("data");
+static u8 ddr3code __section("data");
 static u8 somcode __section("data");
 
 static void board_get_coding_straps(void)
@@ -150,6 +151,7 @@ static void board_get_coding_straps(void)
 	}
 
 	brdcode = 0;
+	ddr3code = 0;
 	somcode = 0;
 
 	ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
@@ -158,13 +160,34 @@ static void board_get_coding_straps(void)
 	for (i = 0; i < ret; i++)
 		somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
 
+	ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
+					      gpio, ARRAY_SIZE(gpio),
+					      GPIOD_IS_IN);
+	for (i = 0; i < ret; i++)
+		ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
 	ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
 					      gpio, ARRAY_SIZE(gpio),
 					      GPIOD_IS_IN);
 	for (i = 0; i < ret; i++)
 		brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
 
-	printf("Code:  SoM:rev=%d Board:rev=%d\n", somcode, brdcode);
+	printf("Code:  SoM:rev=%d,ddr3=%d Board:rev=%d\n",
+		somcode, ddr3code, brdcode);
+}
+
+int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
+					 const char *name)
+{
+	if (ddr3code == 2 &&
+	    !strcmp(name, "st,ddr3-1066-888-bin-g-1x4gb-533mhz"))
+		return 0;
+
+	if (ddr3code == 3 &&
+	    !strcmp(name, "st,ddr3-1066-888-bin-g-2x4gb-533mhz"))
+		return 0;
+
+	return -EINVAL;
 }
 
 int board_early_init_f(void)
@@ -537,6 +560,7 @@ int board_late_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 	env_set_ulong("dh_som_rev", somcode);
 	env_set_ulong("dh_board_rev", brdcode);
+	env_set_ulong("dh_ddr3_code", ddr3code);
 #endif
 
 	return 0;
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index 81222ce444..415bb7111b 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -14,6 +14,7 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its"
 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index e75ed1a932..0b25098d89 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -14,6 +14,7 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its"
 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH V2 4/6] ram: stm32mp1: Add support for multiple configs
  2020-04-10 18:55 ` [PATCH V2 4/6] ram: stm32mp1: Add support for multiple configs Marek Vasut
@ 2020-04-21 17:57   ` Patrick DELAUNAY
  0 siblings, 0 replies; 14+ messages in thread
From: Patrick DELAUNAY @ 2020-04-21 17:57 UTC (permalink / raw)
  To: u-boot

Dear Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: vendredi 10 avril 2020 20:56
> 
> Add support for multiple DRAM configuration subnodes, while retaining the
> support for a single flat DRAM configuration node. This is useful on systems
> which can be manufactured in multiple configurations and where the DRAM
> configuration can be determined at runtime.
> 
> The code is augmented by a function which can be overridden on board level,
> allowing a match on the configuration node name, very much like the fitImage
> configuration node name matching works. The default match is on the single top-
> level DRAM configuration, if matching on subnodes is required, then this
> board_stm32mp1_ddr_config_name_match() must be overridden.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> ---
> V2: Match on compatible string
> ---
>  drivers/ram/stm32mp1/stm32mp1_ram.c | 39 +++++++++++++++++++++++++----
>  1 file changed, 34 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c
> b/drivers/ram/stm32mp1/stm32mp1_ram.c
> index eb78f1198d..21c220694e 100644
> --- a/drivers/ram/stm32mp1/stm32mp1_ram.c
> +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
> @@ -57,6 +57,33 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t
> mem_speed)
>  	return 0;
>  }
> 
> +__weak int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
> +						const char *name)
> +{
> +	return 0;	/* Always match */
> +}
> +
> +static ofnode stm32mp1_ddr_get_ofnode(struct udevice *dev) {
> +	const char *name;
> +	int name_size;
> +	ofnode node;
> +
> +	node = dev_ofnode(dev);
> +	name = ofnode_get_property(node, "compatible", &name_size);
> +	if (!board_stm32mp1_ddr_config_name_match(dev, name))
> +		return node;
> +
> +	dev_for_each_subnode(node, dev) {
> +		name = ofnode_get_property(node, "compatible", &name_size);
> +
> +		if (!board_stm32mp1_ddr_config_name_match(dev, name))
> +			return node;
> +	}
> +
> +	return ofnode_null();
> +}
> +

I think the ddr node could be the fallback when any subnode exist:
board_stm32mp1_ddr_config_name_match() is only usefull/called
when several configuration exist.

And name_size can be replaced by NULL,

So function can be simplify to:

static ofnode stm32mp1_ddr_get_ofnode(struct udevice *dev) {
	const char *name;
	ofnode node;

	dev_for_each_subnode(node, dev) {
		name = ofnode_get_property(node, "compatible", NULL);

		if (!board_stm32mp1_ddr_config_name_match(dev, name))
			return node;
	}

	return dev_ofnode(dev);
}

>  static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)  {
>  	struct ddr_info *priv = dev_get_priv(dev); @@ -64,6 +91,7 @@ static
> __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
>  	unsigned int idx;
>  	struct clk axidcg;
>  	struct stm32mp1_ddr_config config;
> +	ofnode node = stm32mp1_ddr_get_ofnode(dev);

[...]

> @@ -164,7 +192,8 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
>  	priv->info.size = 0;
>  	return stm32mp1_ddr_setup(dev);
>  #else
> -	priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
> +	ofnode node = stm32mp1_ddr_get_ofnode(dev);
> +	priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
>  	return 0;
>  #endif
>  }
> --
> 2.25.1

For the rest

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>

Thanks

Patrick

^ permalink raw reply	[flat|nested] 14+ messages in thread
* [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR
  2020-04-10 18:55 [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR Marek Vasut
                   ` (4 preceding siblings ...)
  2020-04-10 18:55 ` [PATCH V2 6/6] ARM: stm32: Implement DDR3 coding on DHCOR SoM Marek Vasut
@ 2020-04-22  8:24 ` Patrick DELAUNAY
  2020-05-14  7:27   ` Patrick DELAUNAY
  5 siblings, 1 reply; 14+ messages in thread
From: Patrick DELAUNAY @ 2020-04-22  8:24 UTC (permalink / raw)
  To: u-boot

Dear Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: vendredi 10 avril 2020 20:56
> 
> Add default U-Boot configuration for the DHCOR SoM on AV96 board.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> ---
> V2: No change
> ---
>  configs/stm32mp15_dhcor_basic_defconfig | 138 ++++++++++++++++++++++++
>  1 file changed, 138 insertions(+)
>  create mode 100644 configs/stm32mp15_dhcor_basic_defconfig
> 

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>

Thanks

Patrick

^ permalink raw reply	[flat|nested] 14+ messages in thread
* [PATCH V2 2/6] ARM: stm32: Add board_early_init_f() to SPL
  2020-04-10 18:55 ` [PATCH V2 2/6] ARM: stm32: Add board_early_init_f() to SPL Marek Vasut
@ 2020-04-22  8:26   ` Patrick DELAUNAY
  0 siblings, 0 replies; 14+ messages in thread
From: Patrick DELAUNAY @ 2020-04-22  8:26 UTC (permalink / raw)
  To: u-boot

Dear Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: vendredi 10 avril 2020 20:56
> 
> Add weak implementation of board_early_init_f() hook into the
> STM32MP1 SPL. This can be used to read out e.g. configuration straps before
> initializing the DRAM.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> ---
> V2: No change
> ---
>  arch/arm/mach-stm32mp/spl.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>

Thanks

Patrick

^ permalink raw reply	[flat|nested] 14+ messages in thread
* [PATCH V2 3/6] ARM: stm32: Implement board coding on AV96
  2020-04-10 18:55 ` [PATCH V2 3/6] ARM: stm32: Implement board coding on AV96 Marek Vasut
@ 2020-04-22  8:36   ` Patrick DELAUNAY
  0 siblings, 0 replies; 14+ messages in thread
From: Patrick DELAUNAY @ 2020-04-22  8:36 UTC (permalink / raw)
  To: u-boot

Dear Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: vendredi 10 avril 2020 20:56
> 
> The AV96 board does exist in multiple variants. To cater for all of them, implement
> board code handling. There are two GPIOs which code the type of the board, read
> them out and use the value to pick the correct device tree from an fitImage.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> ---
> V2: No change
> ---
>  arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi    |  3 +
>  .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi   |  1 +
>  arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi    |  9 +++
>  board/dhelectronics/dh_stm32mp1/Kconfig       |  2 +-
>  board/dhelectronics/dh_stm32mp1/board.c       | 61 +++++++++++++++++++
>  .../dh_stm32mp1/u-boot-dhcom.its              | 39 ++++++++++++
>  .../dh_stm32mp1/u-boot-dhcor.its              | 39 ++++++++++++
>  configs/stm32mp15_dhcom_basic_defconfig       |  3 +
>  configs/stm32mp15_dhcor_basic_defconfig       |  3 +
>  include/configs/dh_stm32mp1.h                 | 15 +++++
>  10 files changed, 174 insertions(+), 1 deletion(-)  create mode 100644
> board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
>  create mode 100644 board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
>  create mode 100644 include/configs/dh_stm32mp1.h
> 
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> index eba3588540..fcdc5e6859 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> @@ -19,10 +19,13 @@
>  	};
> 
>  	config {
> +		u-boot,dm-pre-reloc;

No needed to add " u-boot,dm-pre-reloc" for config, it is always available.

>  		u-boot,boot-led = "heartbeat";
>  		u-boot,error-led = "error";
>  		st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
>  		st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
> +		#gpio-cells = <2>;

#gpio-cells, No needed in config, only in gpio-controller

> +		dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15
> 0>;
>  	};
> 
>  	led {
> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
> b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
> index 4207a96618..7ccec95f15 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
> @@ -15,6 +15,7 @@
>  	config {
>  		u-boot,boot-led = "led1";
>  		u-boot,error-led = "led4";
> +		dh,board-coding-gpios = <&gpiog 13 0>, <&gpiod 9 0>;
>  	};
>  };
> 
> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
> b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
> index 02dad81b0b..17a23ae21c 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
> @@ -11,6 +11,15 @@
>  #include "stm32mp157-u-boot.dtsi"
>  #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
> 
> +/ {
> +	u-boot,dm-pre-reloc;
> +	config {
> +		u-boot,dm-pre-reloc;
> +		#gpio-cells = <2>;

Dito: 2 lines not needed

> +		dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
> +	};
> +};
> +
>  &i2c4 {
>  	u-boot,dm-pre-reloc;
>  };

[...]

Few minor remarks on device tree.

Anyway, the rest is OK for me

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>

Thanks

Patrick

> --
> 2.25.1

^ permalink raw reply	[flat|nested] 14+ messages in thread
* [PATCH V2 5/6] ARM: dts: stm32: Rework DDR DT inclusion
  2020-04-10 18:55 ` [PATCH V2 5/6] ARM: dts: stm32: Rework DDR DT inclusion Marek Vasut
@ 2020-04-22  9:06   ` Patrick DELAUNAY
  2020-04-22 11:15     ` Marek Vasut
  0 siblings, 1 reply; 14+ messages in thread
From: Patrick DELAUNAY @ 2020-04-22  9:06 UTC (permalink / raw)
  To: u-boot

Dear Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: vendredi 10 avril 2020 20:56
> 
> Adjust the DDR configuration dtsi such that they only generate the DRAM
> configuration node, the DDR controller node is moved into the stm32mp157-u-
> boot.dtsi itself. This permits including multiple DDR configuration dtsi files in
> board DT.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> ---
> V2: Add compatible string
> ---
>  arch/arm/dts/stm32mp15-ddr.dtsi               | 358 +++++++++++-------
>  .../dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi   |   1 +
>  .../dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi   |   1 +
>  arch/arm/dts/stm32mp157-u-boot.dtsi           |  25 ++
>  4 files changed, 248 insertions(+), 137 deletions(-)
> 
> diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
> index 38f29bb789..026237b088 100644
> --- a/arch/arm/dts/stm32mp15-ddr.dtsi
> +++ b/arch/arm/dts/stm32mp15-ddr.dtsi
> @@ -2,153 +2,237 @@
>  /*
>   * Copyright : STMicroelectronics 2018
>   */
> +#include <linux/stringify.h>
> 
> -/ {
> -	soc {
> -		ddr: ddr at 5a003000 {
> -			u-boot,dm-pre-reloc;
> +&ddr {
> +	config-DDR_MEM_COMPATIBLE {
> +		u-boot,dm-pre-reloc;
> -			compatible = "st,stm32mp1-ddr";
> +		compatible = __stringify(st,DDR_MEM_COMPATIBLE);

I have just a concern here, but only for ST ecosystem.

As the DDR_MEM_COMPATIBLE is not generated by CubeMX tools. 

But I will manage it after.....

2 solution; I add a default value.

#ifndef DDR_MEM_COMPATIBLE
#define DDR_MEM_COMPATIBLE ddr-0
#endif

Or don't create sub-node when the COMPATIBLE is absent.

So for this patch:

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>

Thanks

Patrick

^ permalink raw reply	[flat|nested] 14+ messages in thread
* [PATCH V2 6/6] ARM: stm32: Implement DDR3 coding on DHCOR SoM
  2020-04-10 18:55 ` [PATCH V2 6/6] ARM: stm32: Implement DDR3 coding on DHCOR SoM Marek Vasut
@ 2020-04-22  9:08   ` Patrick DELAUNAY
  0 siblings, 0 replies; 14+ messages in thread
From: Patrick DELAUNAY @ 2020-04-22  9:08 UTC (permalink / raw)
  To: u-boot

Hi Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: vendredi 10 avril 2020 20:56
> 
> The DHCOR board does exist in multiple variants with different DDR3 DRAM
> sizes. To cater for all of them, implement DDR3 code handling.
> There are two GPIOs which code the DRAM size populated on the SoM, read
> them out and use the value to pick the correct DDR3 config.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> ---
> V2: Match on compatible string
> ---
>  arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi |  2 ++
> arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi |  2 ++
>  board/dhelectronics/dh_stm32mp1/board.c    | 26 +++++++++++++++++++++-
>  configs/stm32mp15_dhcom_basic_defconfig    |  1 +
>  configs/stm32mp15_dhcor_basic_defconfig    |  1 +
>  5 files changed, 31 insertions(+), 1 deletion(-)
> 

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>

Thanks

Patrick

^ permalink raw reply	[flat|nested] 14+ messages in thread
* [PATCH V2 5/6] ARM: dts: stm32: Rework DDR DT inclusion
  2020-04-22  9:06   ` Patrick DELAUNAY
@ 2020-04-22 11:15     ` Marek Vasut
  0 siblings, 0 replies; 14+ messages in thread
From: Marek Vasut @ 2020-04-22 11:15 UTC (permalink / raw)
  To: u-boot

On 4/22/20 11:06 AM, Patrick DELAUNAY wrote:
> Dear Marek,
> 
>> From: Marek Vasut <marex@denx.de>
>> Sent: vendredi 10 avril 2020 20:56
>>
>> Adjust the DDR configuration dtsi such that they only generate the DRAM
>> configuration node, the DDR controller node is moved into the stm32mp157-u-
>> boot.dtsi itself. This permits including multiple DDR configuration dtsi files in
>> board DT.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>> Cc: Patrick Delaunay <patrick.delaunay@st.com>
>> Cc: Patrice Chotard <patrice.chotard@st.com>
>> ---
>> V2: Add compatible string
>> ---
>>  arch/arm/dts/stm32mp15-ddr.dtsi               | 358 +++++++++++-------
>>  .../dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi   |   1 +
>>  .../dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi   |   1 +
>>  arch/arm/dts/stm32mp157-u-boot.dtsi           |  25 ++
>>  4 files changed, 248 insertions(+), 137 deletions(-)
>>
>> diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
>> index 38f29bb789..026237b088 100644
>> --- a/arch/arm/dts/stm32mp15-ddr.dtsi
>> +++ b/arch/arm/dts/stm32mp15-ddr.dtsi
>> @@ -2,153 +2,237 @@
>>  /*
>>   * Copyright : STMicroelectronics 2018
>>   */
>> +#include <linux/stringify.h>
>>
>> -/ {
>> -	soc {
>> -		ddr: ddr at 5a003000 {
>> -			u-boot,dm-pre-reloc;
>> +&ddr {
>> +	config-DDR_MEM_COMPATIBLE {
>> +		u-boot,dm-pre-reloc;
>> -			compatible = "st,stm32mp1-ddr";
>> +		compatible = __stringify(st,DDR_MEM_COMPATIBLE);
> 
> I have just a concern here, but only for ST ecosystem.
> 
> As the DDR_MEM_COMPATIBLE is not generated by CubeMX tools. 
> 
> But I will manage it after.....
> 
> 2 solution; I add a default value.
> 
> #ifndef DDR_MEM_COMPATIBLE
> #define DDR_MEM_COMPATIBLE ddr-0
> #endif

The other option would be to move the #define DDR_MEM_COMPATIBLE into
board DTS, to let the board specify it's own per-DRAM-config compatible,
on which it will match. E.g.:

#define DDR_MEM_COMPATIBLE ddr-1gib
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
#define DDR_MEM_COMPATIBLE ddr-2gib
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"

Might be a bit better, but it might also lead to a lot of duplication.

^ permalink raw reply	[flat|nested] 14+ messages in thread
* [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR
  2020-04-22  8:24 ` [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR Patrick DELAUNAY
@ 2020-05-14  7:27   ` Patrick DELAUNAY
  0 siblings, 0 replies; 14+ messages in thread
From: Patrick DELAUNAY @ 2020-05-14  7:27 UTC (permalink / raw)
  To: u-boot

Hi Marek,

> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Patrick DELAUNAY
> Sent: mercredi 22 avril 2020 10:25
> 
> Dear Marek,
> 
> > From: Marek Vasut <marex@denx.de>
> > Sent: vendredi 10 avril 2020 20:56
> >
> > Add default U-Boot configuration for the DHCOR SoM on AV96 board.
> >
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Cc: Patrick Delaunay <patrick.delaunay@st.com>
> > Cc: Patrice Chotard <patrice.chotard@st.com>
> > ---
> > V2: No change
> > ---
> >  configs/stm32mp15_dhcor_basic_defconfig | 138
> ++++++++++++++++++++++++
> >  1 file changed, 138 insertions(+)
> >  create mode 100644 configs/stm32mp15_dhcor_basic_defconfig
> >

Applied to u-boot-stm/master, thanks!

With update of Maintainers file agreed with Marek:

----------------- board/dhelectronics/dh_stm32mp1/MAINTAINERS -----------------
index 1511ecb65d..fd70131f9e 100644
@@ -4,4 +4,5 @@ S:	Maintained
 F:	arch/arm/dts/stm32mp15xx-dhcom*
 F:	board/dhelectronics/dh_stm32mp1/
 F:	configs/stm32mp15_dhcom_basic_defconfig
+F:	configs/stm32mp15_dhcor_basic_defconfig
 F:	include/configs/stm32mp1.h

Regards

Patrick

^ permalink raw reply	[flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-05-14  7:27 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-10 18:55 [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR Marek Vasut
2020-04-10 18:55 ` [PATCH V2 2/6] ARM: stm32: Add board_early_init_f() to SPL Marek Vasut
2020-04-22  8:26   ` Patrick DELAUNAY
2020-04-10 18:55 ` [PATCH V2 3/6] ARM: stm32: Implement board coding on AV96 Marek Vasut
2020-04-22  8:36   ` Patrick DELAUNAY
2020-04-10 18:55 ` [PATCH V2 4/6] ram: stm32mp1: Add support for multiple configs Marek Vasut
2020-04-21 17:57   ` Patrick DELAUNAY
2020-04-10 18:55 ` [PATCH V2 5/6] ARM: dts: stm32: Rework DDR DT inclusion Marek Vasut
2020-04-22  9:06   ` Patrick DELAUNAY
2020-04-22 11:15     ` Marek Vasut
2020-04-10 18:55 ` [PATCH V2 6/6] ARM: stm32: Implement DDR3 coding on DHCOR SoM Marek Vasut
2020-04-22  9:08   ` Patrick DELAUNAY
2020-04-22  8:24 ` [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR Patrick DELAUNAY
2020-05-14  7:27   ` Patrick DELAUNAY

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