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([2001:b07:6468:f312:9520:22e6:6416:5c36]) by smtp.gmail.com with ESMTPSA id l18sm2052337wrc.18.2019.09.26.04.06.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Sep 2019 04:06:34 -0700 (PDT) Subject: Re: [PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR To: Sebastian Andrzej Siewior , qemu-devel@nongnu.org References: <20190925214948.22212-1-bigeasy@linutronix.de> From: Paolo Bonzini Openpgp: preference=signencrypt Message-ID: Date: Thu, 26 Sep 2019 13:06:34 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190925214948.22212-1-bigeasy@linutronix.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 25/09/19 23:49, Sebastian Andrzej Siewior wrote: > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ > > +#define CPUD_800_008_EBX_CLZERO (1U << 0) /* CLZERO instruction */ > +#define CPUD_800_008_EBX_XSAVEERPTR (1U << 2) /* Always save/restore FP error pointers */ > #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and Well, there are obvious typos here but I can fix them for you. Which processors have these? Paolo