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References: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de>
	<20181012173047.25420-22-kbastian@mail.uni-paderborn.de>
From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <af15eae9-c2a6-68dd-3570-0e41edd8bf1f@linaro.org>
Date: Sat, 13 Oct 2018 12:45:08 -0700
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Subject: Re: [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store()
 with trans_store()
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To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu
Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org

On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +static bool trans_store(DisasContext *ctx, arg_sb *a, int memop)

gen_store.

>  {
> -    gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
> +    TCGv t0 = tcg_temp_new();
> +    TCGv dat = tcg_temp_new();
> +    gen_get_gpr(t0, a->rs1);
> +    tcg_gen_addi_tl(t0, t0, a->imm);
> +    gen_get_gpr(dat, a->rs2);
> +
> +    if (memop < 0) {
> +        return false;
> +    }

Can't happen.  Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~