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([fe80::c09c:36c8:3301:4457%5]) with mapi id 15.20.2408.024; Wed, 6 Nov 2019 08:33:52 +0000 From: To: , Subject: Re: [PATCH v4 13/20] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Thread-Topic: [PATCH v4 13/20] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Thread-Index: AQHVkW/+ecEbRc4nfkO7skTHWA7uQqd81AsAgAEC2gA= Date: Wed, 6 Nov 2019 08:33:52 +0000 Message-ID: References: <20191102112316.20715-1-tudor.ambarus@microchip.com> <20191102112316.20715-14-tudor.ambarus@microchip.com> <14e9c474-1a92-b8be-12cf-56c7f6d0d696@ti.com> In-Reply-To: <14e9c474-1a92-b8be-12cf-56c7f6d0d696@ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR09CA0167.eurprd09.prod.outlook.com (2603:10a6:800:120::21) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [86.120.239.29] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 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not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: pRRqQharBTXXXtd9PlsM1J/OX9f0ZUe8NPt2stcRgD1Hb0ablJ5qdX+mzG3cDbKWey0yApRRp0LUYuvm7zbQzzS3ZAD7VUvMa8s39T+RUaL4dxWYCEj6uxczv2KQ/xqBJI3aq92xVl1ZyQX1MCEZPrx7yFo47iemJV3rqD7aYErmGkA7pENfdSriq+s32UWfd+mVspLMFO8MzqZNBmCQQx0yUqT0JuAVmun17P2JkHXpTPIsU2otIl8kieoB3Cgz6hkWvsYp69o/pE9nwylsrl9R2FXgIsNuq5ONl5YvsVxxIJqGGQqQMugOd0UCEWOI5J2ruplwfDzCOtO60eK7GUSsXaw85+z9cVrI+VG7whU84hCvhwy5xKUy62rY1WqYk4lPxT1eEybDY4OXXZFRXr+rF0EbZTwSo/dNNJLS3Ji2TlzGqKXTl6vE6f6Wxz89 x-ms-exchange-transport-forked: True Content-ID: <83047FBCF1568C4ABD2AFE824BF8CFCE@namprd11.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 7ce2c41b-bb1f-48c0-538f-08d762940e08 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Nov 2019 08:33:52.8691 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: R3w/DOWlinz7t9fzDhDG4OWXpIM4igYmNxr+7U1mBLFrSxvk9Y6qVlnvIjg2BDqu87zVo1rgidQJZNVIBfwPnoGhL7lgGfkJ3a66djKpt5c= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4063 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191106_003400_346687_5C96E2B7 X-CRM114-Status: GOOD ( 18.47 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard@nod.at, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, miquel.raynal@bootlin.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On 11/05/2019 07:07 PM, Vignesh Raghavendra wrote: > On 02-Nov-19 4:53 PM, Tudor.Ambarus@microchip.com wrote: >> From: Tudor Ambarus >> >> Make sure that when doing a lock() or an unlock() operation we don't clear >> the QE bit from Status Register 2. >> >> JESD216 revB or later offers information about the *default* Status >> Register commands to use (see BFPT DWORDS[15], bits 22:20). In this >> standard, Status Register 1 refers to the first data byte transferred on a >> Read Status (05h) or Write Status (01h) command. Status register 2 refers >> to the byte read using instruction 35h. Status register 2 is the second >> byte transferred in a Write Status (01h) command. >> >> Industry naming and definitions of these Status Registers may differ. >> The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20. >> There are cases in which writing only one byte to the Status Register 1 >> has the side-effect of clearing Status Register 2 and implicitly the Quad >> Enable bit. This side-effect is hit just by the >> BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases. >> > But I see that 1 byte SR1 write still happens as part of > spi_nor_clear_sr_bp() until patch 20/20. So is this only a partial fix? Fixing spi_nor_clear_sr_bp() would mean to add dead code that will be removed anyway with patch 20/20. This patch fixes the clearing of the QE bit, while in 20/20 the QE bit is already zero when the one byte SR1 write is used, so the quad mode is not affected. 20/20 fixes indirectly the clearing of all the bits from SR2 but QE bit, because it's already zero. I would say it's not a partial fix, but a different bug. There are different angles to look at this, I chose the modifying of the quad mode angle. Given the two arguments from above (avoid adding dead code and changing of quad mode approach), I would prefer to keep things as they are. But I get your approach too, so if you still want yours, I can do it. Please let me know. > Should this patch be rearranged to appear along with 20/20? Not necessarily (different bugs) but I can bring 20/20 immediately after this one if you want. > > >> Suggested-by: Boris Brezillon >> Signed-off-by: Tudor Ambarus >> --- >> drivers/mtd/spi-nor/spi-nor.c | 120 ++++++++++++++++++++++++++++++++++++++++-- >> include/linux/mtd/spi-nor.h | 3 ++ >> 2 files changed, 118 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c >> index 725dab241271..f96bc80c0ed1 100644 >> --- a/drivers/mtd/spi-nor/spi-nor.c >> +++ b/drivers/mtd/spi-nor/spi-nor.c >> @@ -959,12 +959,19 @@ static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) >> return spi_nor_wait_till_ready(nor); >> } >> > [...] >> +/** >> * spi_nor_write_sr2() - Write the Status Register 2 using the >> * SPINOR_OP_WRSR2 (3eh) command. >> * @nor: pointer to 'struct spi_nor'. >> @@ -3634,19 +3723,38 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, >> break; >> >> case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: >> + /* >> + * Writing only one byte to the Status Register has the >> + * side-effect of clearing Status Register 2. >> + */ >> case BFPT_DWORD15_QER_SR2_BIT1_NO_RD: >> + /* >> + * Read Configuration Register (35h) instruction is not >> + * supported. >> + */ >> + nor->flags |= SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR; > Since SNOR_F_HAS_16BIT_SR is set by default in > spi_nor_info_init_params(), no need to set the flag here again > I did this on purpose. I set SNOR_F_HAS_16BIT_SR here based on SFDP standard, I want to indicate where the standard requires the 16 bit SR write . spi_nor_info_init_params() initializes data based on info, but that data can be overwritten (even with the same data) when parsing SFDP. Thanks, ta ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/