From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753552AbcL3KHE (ORCPT ); Fri, 30 Dec 2016 05:07:04 -0500 Received: from mail-lf0-f45.google.com ([209.85.215.45]:34451 "EHLO mail-lf0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751431AbcL3KHC (ORCPT ); Fri, 30 Dec 2016 05:07:02 -0500 Subject: Re: [PATCH 1/2] arm64: dma_mapping: allow PCI host driver to limit DMA mask To: Nikita Yushchenko , Catalin Marinas , Will Deacon , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, Simon Horman , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org References: <1483044304-2085-1-git-send-email-nikita.yoush@cogentembedded.com> Cc: artemi.ivanov@cogentembedded.com, linux-kernel@vger.kernel.org From: Sergei Shtylyov Message-ID: Date: Fri, 30 Dec 2016 13:06:58 +0300 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/30/2016 12:46 PM, Sergei Shtylyov wrote: >> It is possible that PCI device supports 64-bit DMA addressing, and thus >> it's driver sets device's dma_mask to DMA_BIT_MASK(64), however PCI host > > Its. > >> bridge has limitations on inbound transactions addressing. Example of >> such setup is NVME > > Isn't it called NVMe? > >> SSD device connected to RCAR PCIe controller. > > R=Car. Sorry, R-Car. :-) [...] MBR, Sergei From mboxrd@z Thu Jan 1 00:00:00 1970 From: sergei.shtylyov@cogentembedded.com (Sergei Shtylyov) Date: Fri, 30 Dec 2016 13:06:58 +0300 Subject: [PATCH 1/2] arm64: dma_mapping: allow PCI host driver to limit DMA mask In-Reply-To: References: <1483044304-2085-1-git-send-email-nikita.yoush@cogentembedded.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 12/30/2016 12:46 PM, Sergei Shtylyov wrote: >> It is possible that PCI device supports 64-bit DMA addressing, and thus >> it's driver sets device's dma_mask to DMA_BIT_MASK(64), however PCI host > > Its. > >> bridge has limitations on inbound transactions addressing. Example of >> such setup is NVME > > Isn't it called NVMe? > >> SSD device connected to RCAR PCIe controller. > > R=Car. Sorry, R-Car. :-) [...] MBR, Sergei