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Date: Mon, 25 Apr 2016 15:06:07 +0100
From: "Maciej W. Rozycki" <macro@imgtec.com>
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Subject: Re: [Qemu-devel] [PATCH v5 5/9] target-mips: Activate IEEE 274-2008
 signaling NaN bit meaning
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To: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, proljc@gmail.com, kbastian@mail.uni-paderborn.de, mark.cave-ayland@ilande.co.uk, agraf@suse.de, blauwirbel@gmail.com, jcmvbkbc@gmail.com, aleksandar.markovic@imgtec.com, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, petar.jovanovic@imgtec.com, pbonzini@redhat.com, miodrag.dinic@imgtec.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, Leon Alrae <leon.alrae@imgtec.com>, afaerber@suse.de, Aurelien Jarno <aurelien@aurel32.net>, rth@twiddle.net

On Mon, 18 Apr 2016, Aleksandar Markovic wrote:

> Functions mips_cpu_reset() and msa_reset() are updated so that flag
> snan_bit_is_one is properly set for any Mips FPU/MSA configuration.
> For main FPUs, CPUs with FCR31's FCR31_NAN2008 bit set will invoke
> set_snan_bit_is_one(0). For MSA, as it is IEEE 274-2008 compliant
> from it inception, set_snan_bit_is_one(0) will always be invoked.

 I have skimmed over the series -- have you lost MIPSr3 support (writable 
FCSR ABS2008 and NAN2008 bits) in porting?

  Maciej