From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Stabellini Subject: Re: [PATCH v4 13/16] xen/arm: Add support for GIC v3 Date: Tue, 3 Jun 2014 11:46:38 +0100 Message-ID: References: <1401100009-7326-1-git-send-email-vijay.kilari@gmail.com> <1401100009-7326-14-git-send-email-vijay.kilari@gmail.com> <1401785663.8841.38.camel@kazak.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1401785663.8841.38.camel@kazak.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: vijay.kilari@gmail.com, Stefano Stabellini , Prasun.Kapoor@caviumnetworks.com, Vijaya Kumar K , julien.grall@linaro.org, xen-devel@lists.xen.org, marc.zyngier@arm.com, stefano.stabellini@citrix.com List-Id: xen-devel@lists.xenproject.org On Tue, 3 Jun 2014, Ian Campbell wrote: > > > +static void gicv3_restore_state(const struct vcpu *v) > > > +{ > > > + gicv3_restore_lr(gicv3_info.nr_lrs, v); > > > + restore_aprn_regs(&v->arch.gic); > > > + WRITE_SYSREG32(v->arch.gic.v3.vmcr, ICH_VMCR_EL2); > > > +} > > > > Shouldn't we restore vmcr first? Before writing to the LRs? > > Can you remind me of the dependency? The ICH_VMCR_EL2 settings affect the LRs. For example VEOIM (bit 9), VFIQEn (bit 3), VAckCtl (bit 2), VENG1 (bit 1) and VENG0 (bit 0).