From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758114AbbCDE0V (ORCPT ); Tue, 3 Mar 2015 23:26:21 -0500 Received: from fbr03.mfg.siteprotect.com ([64.26.60.138]:60503 "EHLO fbr03.mfg.siteprotect.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757466AbbCDE0U (ORCPT ); Tue, 3 Mar 2015 23:26:20 -0500 X-Greylist: delayed 577 seconds by postgrey-1.27 at vger.kernel.org; Tue, 03 Mar 2015 23:26:20 EST Date: Tue, 3 Mar 2015 23:16:57 -0500 (EST) From: Vince Weaver X-X-Sender: vince@pianoman.cluster.toy To: mingo@kernel.org, vikas.shivappa@linux.intel.com, hpa@zytor.com, acme@kernel.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, acme@redhat.com, torvalds@linux-foundation.org, matt.fleming@intel.com, kanaka.d.juvva@intel.com, jolsa@redhat.com, peterz@infradead.org Subject: Re: [tip:perf/x86] perf/x86/intel: Support task events with Intel CQM In-Reply-To: Message-ID: References: <1422038748-21397-8-git-send-email-matt@codeblueprint.co.uk> User-Agent: Alpine 2.10 (DEB 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-CTCH-Spam: Unknown X-CTCH-RefID: str=0001.0A020205.54F6872A.0113,ss=1,re=0.001,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 25 Feb 2015, tip-bot for Matt Fleming wrote: > diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h > index 1e3cd07..3c8b45d 100644 > --- a/include/uapi/linux/perf_event.h > +++ b/include/uapi/linux/perf_event.h > @@ -32,6 +32,7 @@ enum perf_type_id { > PERF_TYPE_HW_CACHE = 3, > PERF_TYPE_RAW = 4, > PERF_TYPE_BREAKPOINT = 5, > + PERF_TYPE_INTEL_CQM = 6, > > PERF_TYPE_MAX, /* non-ABI */ > }; I thought the rule was no adding support for things in perf_event unless they were sufficiently generic as to be cross-architecture. Having a high-level event type with "intel" in the name seems awfully specific. Vince