Re: [PATCH 3/7] x86/intel_rdt: Support cache bit mask for Intel CAT

From: Vikas Shivappa <vikas.shivappa@intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Vikas Shivappa <vikas.shivappa@intel.com>,
	Vikas Shivappa <vikas.shivappa@linux.intel.com>,
	linux-kernel@vger.kernel.org, x86@kernel.org, hpa@zytor.com,
	tglx@linutronix.de, mingo@kernel.org, tj@kernel.org,
	Matt Fleming <matt.fleming@intel.com>,
	"Auld, Will" <will.auld@intel.com>,
	peter.zijlstra@intel.com, h.peter.anvin@intel.com, "Juvva,
	Kanaka D" <kanaka.d.juvva@intel.com>
Subject: Re: [PATCH 3/7] x86/intel_rdt: Support cache bit mask for Intel CAT
Date: Wed, 6 May 2015 11:09:08 -0700 (PDT)	[thread overview]
Message-ID: <alpine.DEB.2.10.1505061108380.30862@vshiva-Udesk> (raw)
In-Reply-To: <20150506081143.GV23123@twins.programming.kicks-ass.net>

On Wed, 6 May 2015, Peter Zijlstra wrote:

> On Mon, May 04, 2015 at 10:30:15AM -0700, Vikas Shivappa wrote:
>> Will fix the whitespace issues (including before return) or other possible
>> coding convention issues.
>>
>> It could be more of a common sense to have this in checkpatch rather that
>> manually having to pointing out. If you want to have fun with that go for it
>> though.
>
> My main objection was that your coding style is entirely inconsistent
> with itself.
>
> Sometimes you have a whitespace before return, sometimes you do not.
>
> Sometimes you have exit labels with locks, sometimes you do not.
>
> etc..
>
> Pick one stick to it; although we'd all much prefer if you pick the one
> that's common to the kernel.

Will fix the convention issues.

Thanks,
Vikas

>