From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755549AbbG3SQz (ORCPT ); Thu, 30 Jul 2015 14:16:55 -0400 Received: from mga01.intel.com ([192.55.52.88]:33177 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752071AbbG3SQx (ORCPT ); Thu, 30 Jul 2015 14:16:53 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,578,1432623600"; d="scan'208";a="758630225" Date: Thu, 30 Jul 2015 11:16:50 -0700 (PDT) From: Vikas Shivappa X-X-Sender: vikas@vshiva-Udesk To: Peter Zijlstra cc: Vikas Shivappa , linux-kernel@vger.kernel.org, vikas.shivappa@intel.com, x86@kernel.org, hpa@zytor.com, tglx@linutronix.de, mingo@kernel.org, tj@kernel.org, matt.fleming@intel.com, will.auld@intel.com, glenn.p.williamson@intel.com, kanaka.d.juvva@intel.com Subject: Re: [PATCH 7/9] x86/intel_rdt: Implement scheduling support for Intel RDT In-Reply-To: <20150729134959.GW25159@twins.programming.kicks-ass.net> Message-ID: References: <1435789270-27010-1-git-send-email-vikas.shivappa@linux.intel.com> <1435789270-27010-8-git-send-email-vikas.shivappa@linux.intel.com> <20150729134959.GW25159@twins.programming.kicks-ass.net> User-Agent: Alpine 2.10 (DEB 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 29 Jul 2015, Peter Zijlstra wrote: > On Wed, Jul 01, 2015 at 03:21:08PM -0700, Vikas Shivappa wrote: >> diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h >> index 3ad426c..78df3d7 100644 >> --- a/arch/x86/include/asm/intel_rdt.h >> +++ b/arch/x86/include/asm/intel_rdt.h >> @@ -4,10 +4,16 @@ >> #ifdef CONFIG_CGROUP_RDT >> >> #include >> +#include >> + >> #define MAX_CBM_LENGTH 32 >> #define IA32_L3_CBM_BASE 0xc90 >> #define CBM_FROM_INDEX(x) (IA32_L3_CBM_BASE + x) >> >> +DECLARE_PER_CPU(struct intel_pqr_state, pqr_state); > > You don't think this should be in rdt_common.h ? Sounds good. > >> diff --git a/arch/x86/include/asm/rdt_common.h b/arch/x86/include/asm/rdt_common.h >> new file mode 100644 >> index 0000000..01502c5 >> --- /dev/null >> +++ b/arch/x86/include/asm/rdt_common.h >> @@ -0,0 +1,25 @@ >> +#ifndef _X86_RDT_H_ >> +#define _X86_RDT_H_ >> + >> +#define MSR_IA32_PQR_ASSOC 0x0c8f >> + >> +/** >> + * struct intel_pqr_state - State cache for the PQR MSR >> + * @rmid: The cached Resource Monitoring ID >> + * @closid: The cached Class Of Service ID >> + * @rmid_usecnt: The usage counter for rmid >> + * >> + * The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the >> + * lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always >> + * contains both parts, so we need to cache them. >> + * >> + * The cache also helps to avoid pointless updates if the value does >> + * not change. >> + */ >> +struct intel_pqr_state { >> + u32 rmid; >> + u32 closid; >> + int rmid_usecnt; >> +}; >> + >> +#endif > > So why not call this file PQR something or other? That's all there is. Well , had this to have things common between the cqm code and the other code. I see right now we dont put anything else here other than pqr. Will fix this now and change this later to rdt_common when i add more thigs in really then. > >> diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h >> index 751bf4b..9149577 100644 >> --- a/arch/x86/include/asm/switch_to.h >> +++ b/arch/x86/include/asm/switch_to.h >> @@ -8,6 +8,9 @@ struct tss_struct; >> void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, >> struct tss_struct *tss); >> >> +#include >> +#define finish_arch_switch(prev) intel_rdt_sched_in() > > Right, so please stuff that in __switch_to(), will fix. I think I can kill > finish_arch_switch() entirely. > what about other architectures using them ? Thanks, Vikas >