From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754291AbbHDUzp (ORCPT ); Tue, 4 Aug 2015 16:55:45 -0400 Received: from mga02.intel.com ([134.134.136.20]:23674 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753572AbbHDUzd (ORCPT ); Tue, 4 Aug 2015 16:55:33 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,611,1432623600"; d="scan'208";a="742190260" Date: Tue, 4 Aug 2015 13:41:15 -0700 (PDT) From: Vikas Shivappa X-X-Sender: vikas@vshiva-Udesk To: Peter Zijlstra cc: Vikas Shivappa , linux-kernel@vger.kernel.org, vikas.shivappa@intel.com, x86@kernel.org, hpa@zytor.com, tglx@linutronix.de, mingo@kernel.org, tj@kernel.org, matt.fleming@intel.com, will.auld@intel.com, glenn.p.williamson@intel.com, kanaka.d.juvva@intel.com Subject: Re: [PATCH 3/9] x86/intel_rdt: Cache Allocation documentation and cgroup usage guide In-Reply-To: <20150728145429.GQ25159@twins.programming.kicks-ass.net> Message-ID: References: <1435789270-27010-1-git-send-email-vikas.shivappa@linux.intel.com> <1435789270-27010-4-git-send-email-vikas.shivappa@linux.intel.com> <20150728145429.GQ25159@twins.programming.kicks-ass.net> User-Agent: Alpine 2.10 (DEB 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 28 Jul 2015, Peter Zijlstra wrote: > On Wed, Jul 01, 2015 at 03:21:04PM -0700, Vikas Shivappa wrote: > > Please edit this document to have consistent spacing. Its really hard to > read this. Every time I spot a misplaced space my brain stumbles and I > need to restart. Will fix all the spacing and other indentions issues mentioned. Thanks for pointing them all out. Although the other documents I see dont have a consistent format completely which is what confused me, this format would be better. >> + >> +The following considerations are done for the PQR MSR write so that it >> +has minimal impact on scheduling hot path: >> +- This path doesnt exist on any non-intel platforms. > > !x86 I think you mean, its entirely possible to have the code present > on AMD systems for instance. > >> +- On Intel platforms, this would not exist by default unless CGROUP_RDT >> +is enabled. > > You can enable this just fine on AMD machines. The cache alloc code is under CPU_SUP_INTEL .. Thanks, Vikas