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From: Peter Antoine <peter.antoine@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Davies, Devon" <devon.davies@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v4] drm/i915/mocs: Program MOCS for all engines on init
Date: Tue, 12 Apr 2016 12:52:24 +0100 (BST)	[thread overview]
Message-ID: <alpine.DEB.2.10.1604121251530.3268@peterant-linux2> (raw)
In-Reply-To: <alpine.DEB.2.10.1603220901280.8501@peterant-linux2>

Chris,

If the test is ok, can you review-by this patch.

Thanks,
Peter.

On Tue, 22 Mar 2016, Peter Antoine wrote:

> Chris.
>
> Can these patches be reviewed without the tests or are they blocked waiting 
> for the tests.
>
> Are the patches acceptable?
>
> Thanks,
> Peter.
>
> On Tue, 15 Mar 2016, Peter Antoine wrote:
>
>> Chris,
>> 
>> Testcases are underway, validation are working on them.
>> 
>> Peter.
>> 
>> On Tue, 15 Mar 2016, Chris Wilson wrote:
>> 
>>> On Mon, Mar 14, 2016 at 03:11:02PM +0000, Peter Antoine wrote:
>>>> Allow for the MOCS to be programmed for all engines.
>>>> Currently we program the MOCS when the first render batch
>>>> goes through. This works on most platforms but fails on
>>>> platforms that do not run a render batch early,
>>>> i.e. headless servers. The patch now programs all initialised engines
>>>> on init and the RCS is programmed again within the initial batch. This
>>>> is done for predictable consistency with regards to the hardware
>>>> context.
>>>> 
>>>> Hardware context loading sets the values of the MOCS for RCS
>>>> and L3CC. Programming them from within the batch makes sure that
>>>> the render context is valid, no matter what the previous state of
>>>> the saved-context was.
>>>> 
>>>> v2: posted correct version to the mailing list.
>>>> v3: moved programming to within engine->init_hw() (Chris Wilson)
>>>> v4: code formatting and white-space changes. (Chris Wilson)
>>>> 
>>>> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
>>> 
>>> So testcase?
>>> 
>>> Execute a bunch of MI_STORE_REGISTER_MEM on the various rings in a fresh
>>> context each time and confirm the ABI for the first N locations.
>>> 
>>> Repeat across suspend/resume (i.e. make sure the context image maintain
>>> the register state). Then verify that freshly constructed contexts also
>>> have the correct settings after resume.
>>> -Chris
>>> 
>>> 
>> 
>> --
>>   Peter Antoine (Android Graphics Driver Software Engineer)
>>   ---------------------------------------------------------------------
>>   Intel Corporation (UK) Limited
>>   Registered No. 1134945 (England)
>>   Registered Office: Pipers Way, Swindon SN3 1RJ
>>   VAT No: 860 2173 47
>> 
>
> --
>   Peter Antoine (Android Graphics Driver Software Engineer)
>   ---------------------------------------------------------------------
>   Intel Corporation (UK) Limited
>   Registered No. 1134945 (England)
>   Registered Office: Pipers Way, Swindon SN3 1RJ
>   VAT No: 860 2173 47
>

--
    Peter Antoine (Android Graphics Driver Software Engineer)
    ---------------------------------------------------------------------
    Intel Corporation (UK) Limited
    Registered No. 1134945 (England)
    Registered Office: Pipers Way, Swindon SN3 1RJ
    VAT No: 860 2173 47
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Intel-gfx mailing list
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  parent reply	other threads:[~2016-04-12 11:52 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-14 15:11 [PATCH v4] drm/i915/mocs: Program MOCS for all engines on init Peter Antoine
2016-03-14 15:31 ` ✗ Fi.CI.BAT: failure for drm/i915/mocs: Program MOCS for all engines on init (rev6) Patchwork
2016-03-15 10:15 ` [PATCH v4] drm/i915/mocs: Program MOCS for all engines on init Chris Wilson
2016-03-15 14:40   ` Peter Antoine
2016-03-22  9:02     ` Peter Antoine
2016-03-22  9:36       ` Chris Wilson
2016-04-12 11:52       ` Peter Antoine [this message]
2016-04-13 13:52         ` Chris Wilson

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