From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59358) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coywF-0002QJ-2q for qemu-devel@nongnu.org; Fri, 17 Mar 2017 16:57:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1coywB-0003vz-W6 for qemu-devel@nongnu.org; Fri, 17 Mar 2017 16:57:31 -0400 Received: from mail.kernel.org ([198.145.29.136]:50228) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1coywB-0003vN-Q1 for qemu-devel@nongnu.org; Fri, 17 Mar 2017 16:57:27 -0400 Date: Fri, 17 Mar 2017 13:57:22 -0700 (PDT) From: Stefano Stabellini In-Reply-To: <1e1d1637-1cf8-2ad4-36e2-342aa21b100d@redhat.com> Message-ID: References: <1489750157-17401-1-git-send-email-tianyu.lan@intel.com> <1e1d1637-1cf8-2ad4-36e2-342aa21b100d@redhat.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Subject: Re: [Qemu-devel] [RFC PATCH 0/4] Qemu: Add Xen vIOMMU support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: Lan Tianyu , qemu-devel@nongnu.org, xen-devel@lists.xensource.com, chao.gao@intel.com, kevin.tian@intel.com, anthony.perard@citrix.com, ehabkost@redhat.com, marcel@redhat.com, mst@redhat.com, rth@twiddle.net, sstabellini@kernel.organthony.perard@citrix.com On Fri, 17 Mar 2017, Paolo Bonzini wrote: > On 17/03/2017 12:29, Lan Tianyu wrote: > > This patchset is to add Xen vIOMMU device model and handle > > irq remapping stuffs. Xen vIOMMU emulation is in the Xen hypervisor > > and the new device module in Qemu works as hypercall wrappers to > > create and destroy vIOMMU in hypervisor. > > > > Xen only supports emulated I440 and so we enable vIOMMU with emulated > > I440 chipset. This works on Linux and Windows guest. > > Any plans to change this? Why is Xen not able to use Q35 with Intel > IOMMU, with only special hooks for interrupt remapping? CC'ing Anthony that worked on it in the past > > Chao Gao (4): > > I440: Allow adding sysbus devices with -device on I440 > > Xen: add a dummy vIOMMU to create/destroy vIOMMU in Xen > > xen-pt: bind/unbind interrupt remapping format MSI > > msi: taking interrupt format into consideration during judging a pirq > > is binded with a event channel > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Stabellini Subject: Re: [RFC PATCH 0/4] Qemu: Add Xen vIOMMU support Date: Fri, 17 Mar 2017 13:57:22 -0700 (PDT) Message-ID: References: <1489750157-17401-1-git-send-email-tianyu.lan@intel.com> <1e1d1637-1cf8-2ad4-36e2-342aa21b100d@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1e1d1637-1cf8-2ad4-36e2-342aa21b100d@redhat.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: Paolo Bonzini Cc: Lan Tianyu , kevin.tian@intel.com, xen-devel@lists.xensource.com, ehabkost@redhat.com, mst@redhat.com, qemu-devel@nongnu.org, marcel@redhat.com, sstabellini@kernel.org, anthony.perard@citrix.com, rth@twiddle.net, chao.gao@intel.com List-Id: xen-devel@lists.xenproject.org T24gRnJpLCAxNyBNYXIgMjAxNywgUGFvbG8gQm9uemluaSB3cm90ZToKPiBPbiAxNy8wMy8yMDE3 IDEyOjI5LCBMYW4gVGlhbnl1IHdyb3RlOgo+ID4gVGhpcyBwYXRjaHNldCBpcyB0byBhZGQgWGVu IHZJT01NVSBkZXZpY2UgbW9kZWwgYW5kIGhhbmRsZQo+ID4gaXJxIHJlbWFwcGluZyBzdHVmZnMu IFhlbiB2SU9NTVUgZW11bGF0aW9uIGlzIGluIHRoZSBYZW4gaHlwZXJ2aXNvcgo+ID4gYW5kIHRo ZSBuZXcgZGV2aWNlIG1vZHVsZSBpbiBRZW11IHdvcmtzIGFzIGh5cGVyY2FsbCB3cmFwcGVycyB0 bwo+ID4gY3JlYXRlIGFuZCBkZXN0cm95IHZJT01NVSBpbiBoeXBlcnZpc29yLgo+ID4gCj4gPiBY ZW4gb25seSBzdXBwb3J0cyBlbXVsYXRlZCBJNDQwIGFuZCBzbyB3ZSBlbmFibGUgdklPTU1VIHdp dGggZW11bGF0ZWQKPiA+IEk0NDAgY2hpcHNldC4gVGhpcyB3b3JrcyBvbiBMaW51eCBhbmQgV2lu ZG93cyBndWVzdC4KPiAKPiBBbnkgcGxhbnMgdG8gY2hhbmdlIHRoaXM/ICBXaHkgaXMgWGVuIG5v dCBhYmxlIHRvIHVzZSBRMzUgd2l0aCBJbnRlbAo+IElPTU1VLCB3aXRoIG9ubHkgc3BlY2lhbCBo b29rcyBmb3IgaW50ZXJydXB0IHJlbWFwcGluZz8KCkNDJ2luZyBBbnRob255IHRoYXQgd29ya2Vk IG9uIGl0IGluIHRoZSBwYXN0CgoKPiA+IENoYW8gR2FvICg0KToKPiA+ICAgSTQ0MDogQWxsb3cg YWRkaW5nIHN5c2J1cyBkZXZpY2VzIHdpdGggLWRldmljZSBvbiBJNDQwCj4gPiAgIFhlbjogYWRk IGEgZHVtbXkgdklPTU1VIHRvIGNyZWF0ZS9kZXN0cm95IHZJT01NVSBpbiBYZW4KPiA+ICAgeGVu LXB0OiBiaW5kL3VuYmluZCBpbnRlcnJ1cHQgcmVtYXBwaW5nIGZvcm1hdCBNU0kKPiA+ICAgbXNp OiB0YWtpbmcgaW50ZXJydXB0IGZvcm1hdCBpbnRvIGNvbnNpZGVyYXRpb24gZHVyaW5nIGp1ZGdp bmcgYSBwaXJxCj4gPiAgICAgaXMgYmluZGVkIHdpdGggYSBldmVudCBjaGFubmVsCj4gCgpfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpYZW4tZGV2ZWwgbWFp bGluZyBsaXN0Clhlbi1kZXZlbEBsaXN0cy54ZW4ub3JnCmh0dHBzOi8vbGlzdHMueGVuLm9yZy94 ZW4tZGV2ZWwK