Re: [RFC v2]Proposal to allow setting up shared memory areas between VMs from xl config file

From: Stefano Stabellini <sstabellini@kernel.org>
To: Julien Grall <julien.grall@arm.com>
Cc: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>,
	Stefano Stabellini <sstabellini@kernel.org>,
	Wei Liu <wei.liu2@citrix.com>, Zhongze Liu <blackskygg@gmail.com>,
	Ian Jackson <ian.jackson@eu.citrix.com>,
	edgari@xilinx.com, xen-devel@lists.xenproject.org,
	Jarvis Roach <Jarvis.Roach@dornerworks.com>
Subject: Re: [RFC v2]Proposal to allow setting up shared memory areas between VMs from xl config file
Date: Fri, 23 Jun 2017 11:21:12 -0700 (PDT)	[thread overview]
Message-ID: <alpine.DEB.2.10.1706231108130.12819@sstabellini-ThinkPad-X260> (raw)
In-Reply-To: <e1f98758-377b-2ea4-31f5-1e0435264fc4@arm.com>

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On Fri, 23 Jun 2017, Julien Grall wrote:
> Hi,
> 
> On 22/06/17 22:05, Stefano Stabellini wrote:
> > > When we encounter an id IDx during "xl create":
> > > 
> > >   + If it’s not under /local/shared_mem:
> > >     + If the corresponding entry has a "master" tag, create the
> > >       corresponding entries for IDx in xenstore
> > >     + If there isn't a "master" tag, say error.
> > > 
> > >   + If it’s found under /local/shared_mem:
> > >     + If the corresponding entry has a "master" tag, say error
> > >     + If there isn't a "master" tag, map the pages to the newly
> > >       created domain, and add the current domain and necessary information
> > >       under /local/shared_mem/IDx/slaves.
> > 
> > Aside from using "gfn" instead of gmfn everywhere, I think it looks
> > pretty good.
> > 
> > I would leave out permissions and cacheability attributes from this
> > version of the work. I would just add a note saying that memory will be
> > mapped as RW regular cacheable RAM. Other permissions and cacheability
> > will be possible, but they are not implemented yet.
> 
> Well, I think we should design the interface correctly from the beginning to
> facilitate future extension.

Which interface are you speaking about?

I don't think we should attemp to write how the hypercall interface
might look like in the future to support setting permissions and
cacheability attributes.

> Also, you need to clarify what you mean by "regular cacheable RAM". Are they
> write-through, write-back...? But, on ARM, this would only be the caching
> attribute in stage-2 page table. The final caching, memory type, shareability
> would be a combination of stage-2 and stage-1 attributes.

The very same that is used today for the ram of virtual machines, do we
need to say any more than that? (For ARM, p2m_ram_rw and MATTR_MEM,
LPAE_SH_INNER. For stage1, we should refer to
xen/include/public/arch-arm.h.)

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