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Date: Thu, 23 Jun 2016 12:16:20 +0200 (CEST)
From: Thomas Gleixner <tglx@linutronix.de>
To: Zhaoyang Huang <zhaoyang.huang@linaro.org>
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Subject: Re: [RESEND PATCH v2 2/2] power/idle: enhance the precision of
 sleep_length
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On Thu, 23 Jun 2016, Zhaoyang Huang wrote:
> On 23 June 2016 at 16:35, Thomas Gleixner <tglx@linutronix.de> wrote:
> >> Hi, Thomas. If the entry,exit,min time of one idle state sums up to
> >> 500us in some platform, the 100us callback which should be common as
> >> caused by cache miss would also generate 20% imprecision. Don't you
> >
> > A cache miss is causing a 100us callback? What are you talking about?
> >
> By a serials of memory access which maybe missed on cache all. Anyway,
> we can require the callback not to introduce schedule etc, but can not
> ask them to ensure their own executing time, which they can not
> control.

I really do not understand what you are trying to solve. If the enter to idle
code is delayed by cache misses for 100us then you have other serious problems
than the accuracy of that time stamp.

Thanks,

	tglx