From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752295AbcKRIy0 (ORCPT ); Fri, 18 Nov 2016 03:54:26 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:51193 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751139AbcKRIyY (ORCPT ); Fri, 18 Nov 2016 03:54:24 -0500 Date: Fri, 18 Nov 2016 09:49:34 +0100 (CET) From: Thomas Gleixner To: Ingo Molnar cc: Kyle Huey , "Robert O'Callahan" , Andy Lutomirski , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Paolo Bonzini , =?ISO-8859-2?Q?Radim_Kr=E8m=E1=F8?= , Jeff Dike , Richard Weinberger , Alexander Viro , Shuah Khan , Dave Hansen , Borislav Petkov , Peter Zijlstra , Boris Ostrovsky , Len Brown , "Rafael J. Wysocki" , Dmitry Safonov , David Matlack , Nadav Amit , linux-kernel@vger.kernel.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, linux-fsdevel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v12 6/7] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID In-Reply-To: <20161118081444.GC15912@gmail.com> Message-ID: References: <20161117020610.5302-1-khuey@kylehuey.com> <20161117020610.5302-7-khuey@kylehuey.com> <20161118081444.GC15912@gmail.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 18 Nov 2016, Ingo Molnar wrote: > * Kyle Huey wrote: > > + if (test_tsk_thread_flag(prev_p, TIF_NOCPUID) ^ > > + test_tsk_thread_flag(next_p, TIF_NOCPUID)) { > > + set_cpuid_faulting(test_tsk_thread_flag(next_p, TIF_NOCPUID)); > > + } > > + > > Why not cache the required MSR value in the task struct instead? > > That would allow something much more obvious and much faster, like: > > if (prev_p->thread.misc_features_val != next_p->thread.misc_features_val) > wrmsrl(MSR_MISC_FEATURES_ENABLES, next_p->thread.misc_features_val); > > (The TIF flag maintenance is still required to get into __switch_to_xtra().) > > It would also be easy to extend without extra overhead, should any other feature > bit be added to the MSR in the future. I doubt that. There are feature enable bits coming up which are not related to tasks. So if we have switches enabling/disabling global features, then we would be forced to chase all threads in order to update all misc_features thread variables. Surely not what we want to do. Thanks, tglx From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Gleixner Subject: Re: [PATCH v12 6/7] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Date: Fri, 18 Nov 2016 09:49:34 +0100 (CET) Message-ID: References: <20161117020610.5302-1-khuey@kylehuey.com> <20161117020610.5302-7-khuey@kylehuey.com> <20161118081444.GC15912@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Cc: Kyle Huey , Robert O'Callahan , Andy Lutomirski , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Paolo Bonzini , =?ISO-8859-2?Q?Radim_Kr=E8m=E1=F8?= , Jeff Dike , Richard Weinberger , Alexander Viro , Shuah Khan , Dave Hansen , Borislav Petkov , Peter Zijlstra , Boris Ostrovsky , Len Brown , "Rafael J. Wysocki" , Dmitry Safonov , David Matlack , N To: Ingo Molnar Return-path: Received: from Galois.linutronix.de ([146.0.238.70]:51193 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751139AbcKRIyY (ORCPT ); Fri, 18 Nov 2016 03:54:24 -0500 In-Reply-To: <20161118081444.GC15912@gmail.com> Sender: kvm-owner@vger.kernel.org List-ID: On Fri, 18 Nov 2016, Ingo Molnar wrote: > * Kyle Huey wrote: > > + if (test_tsk_thread_flag(prev_p, TIF_NOCPUID) ^ > > + test_tsk_thread_flag(next_p, TIF_NOCPUID)) { > > + set_cpuid_faulting(test_tsk_thread_flag(next_p, TIF_NOCPUID)); > > + } > > + > > Why not cache the required MSR value in the task struct instead? > > That would allow something much more obvious and much faster, like: > > if (prev_p->thread.misc_features_val != next_p->thread.misc_features_val) > wrmsrl(MSR_MISC_FEATURES_ENABLES, next_p->thread.misc_features_val); > > (The TIF flag maintenance is still required to get into __switch_to_xtra().) > > It would also be easy to extend without extra overhead, should any other feature > bit be added to the MSR in the future. I doubt that. There are feature enable bits coming up which are not related to tasks. So if we have switches enabling/disabling global features, then we would be forced to chase all threads in order to update all misc_features thread variables. Surely not what we want to do. Thanks, tglx