From: matthew.gerlach@linux.intel.com
To: Rob Herring <robh@kernel.org>
Cc: atull@opensource.altera.com, moritz.fischer@ettus.com,
linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, mark.rutland@arm.com
Subject: Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP.
Date: Mon, 27 Feb 2017 08:27:49 -0800 (PST) [thread overview]
Message-ID: <alpine.DEB.2.20.1702270822260.13342@mgerlach-VirtualBox> (raw)
In-Reply-To: <20170227143230.b3frg3rg2sdttt64@rob-hp-laptop>
On Mon, 27 Feb 2017, Rob Herring wrote:
Hi Rob,
> On Wed, Feb 15, 2017 at 01:10:37PM -0800, matthew.gerlach@linux.intel.com wrote:
>> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>
>> Device Tree bindings for Altera Partial Reconfiguraion IP?
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> ---
>> Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>>
>> diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>> new file mode 100644
>> index 0000000..ada821f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>> @@ -0,0 +1,12 @@
>> +Altera Partial Reconfiguration IP
>> +
>> +Required properties:
>> +- compatible : should contain "altr,pr-ip"
>
> Kind of generic. There's only one version of h/w?
Fair point on being generic. It does match the published documentation,
but we could be more specific with "altr,a10-pr-ip" because it
really is only for an Arria10.
Matthew Gerlach
>
>> +- reg : base address and size for memory mapped io.
>> +
>> +Example:
>> +
>> + fpga_mgr: fpga-mgr@ff20c000 {
>> + compatible = "altr,pr-ip";
>> + reg = <0xff20c000 0x10>;
>> + };
>> --
>> 2.7.4
>>
>
next prev parent reply other threads:[~2017-02-27 16:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-15 21:10 [PATCH 0/4] Altera Partial Reconfiguration IP matthew.gerlach
2017-02-15 21:10 ` matthew.gerlach-VuQAYsv1563Yd54FQh9/CA
2017-02-15 21:10 ` [PATCH 1/4] fpga: add config complete timeout matthew.gerlach
2017-02-15 21:10 ` matthew.gerlach-VuQAYsv1563Yd54FQh9/CA
2017-02-15 21:10 ` [PATCH 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP matthew.gerlach
2017-02-16 17:35 ` Moritz Fischer
2017-02-16 17:35 ` Moritz Fischer
2017-02-16 22:47 ` matthew.gerlach
2017-02-15 21:10 ` [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP matthew.gerlach
2017-02-15 21:10 ` matthew.gerlach-VuQAYsv1563Yd54FQh9/CA
2017-02-17 13:31 ` Dinh Nguyen
2017-02-17 13:31 ` Dinh Nguyen
2017-02-17 15:20 ` Moritz Fischer
2017-02-27 14:32 ` Rob Herring
2017-02-27 16:27 ` matthew.gerlach [this message]
2017-02-15 21:10 ` [PATCH 4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP matthew.gerlach
2017-02-26 22:51 ` kbuild test robot
2017-02-26 22:51 ` kbuild test robot
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