From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752657AbdLLVmV (ORCPT ); Tue, 12 Dec 2017 16:42:21 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:34468 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752553AbdLLVmU (ORCPT ); Tue, 12 Dec 2017 16:42:20 -0500 Date: Tue, 12 Dec 2017 22:42:14 +0100 (CET) From: Thomas Gleixner To: Andy Lutomirski cc: Dave Hansen , Linus Torvalds , LKML , the arch/x86 maintainers , Peter Zijlstra , Borislav Petkov , Greg KH , Kees Cook , Hugh Dickins , Brian Gerst , Josh Poimboeuf , Denys Vlasenko , Boris Ostrovsky , Juergen Gross , David Laight , Eduardo Valentin , "Liguori, Anthony" , Will Deacon , linux-mm Subject: Re: [patch 13/16] x86/ldt: Introduce LDT write fault handler In-Reply-To: Message-ID: References: <20171212173221.496222173@linutronix.de> <20171212173334.345422294@linutronix.de> <212680b8-6f8d-f785-42fd-61846553570d@intel.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 12 Dec 2017, Andy Lutomirski wrote: > On Tue, Dec 12, 2017 at 12:37 PM, Thomas Gleixner wrote: > > On Tue, 12 Dec 2017, Dave Hansen wrote: > > > >> On 12/12/2017 11:21 AM, Thomas Gleixner wrote: > >> > The only critical interaction is the return to user path (user CS/SS) and > >> > we made sure with the LAR touching that these are precached in the CPU > >> > before we go into fragile exit code. > >> > >> How do we make sure that it _stays_ cached? > >> > >> Surely there is weird stuff like WBINVD or SMI's that can come at very > >> inconvenient times and wipe it out of the cache. > > > > This does not look like cache in the sense of memory cache. It seems to be > > CPU internal state and I just stuffed WBINVD and alternatively CLFLUSH'ed > > the entries after the 'touch' via LAR. Still works. > > > > There *must* be some weird bug in this series. I find it very hard to > believe that x86 CPUs have a magic cache that caches any part of a > not-actually-in-a-segment-register descriptor entry. There is no bug in the code. There was just a bug in my brain which made me fail to see the obvious. See the other mail. Thanks, tglx From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-f197.google.com (mail-wr0-f197.google.com [209.85.128.197]) by kanga.kvack.org (Postfix) with ESMTP id 755946B0069 for ; Tue, 12 Dec 2017 16:42:44 -0500 (EST) Received: by mail-wr0-f197.google.com with SMTP id 55so142343wrx.21 for ; Tue, 12 Dec 2017 13:42:44 -0800 (PST) Received: from Galois.linutronix.de (Galois.linutronix.de. [2a01:7a0:2:106d:700::1]) by mx.google.com with ESMTPS id i143si330722wmd.222.2017.12.12.13.42.43 for (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 12 Dec 2017 13:42:43 -0800 (PST) Date: Tue, 12 Dec 2017 22:42:14 +0100 (CET) From: Thomas Gleixner Subject: Re: [patch 13/16] x86/ldt: Introduce LDT write fault handler In-Reply-To: Message-ID: References: <20171212173221.496222173@linutronix.de> <20171212173334.345422294@linutronix.de> <212680b8-6f8d-f785-42fd-61846553570d@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: owner-linux-mm@kvack.org List-ID: To: Andy Lutomirski Cc: Dave Hansen , Linus Torvalds , LKML , the arch/x86 maintainers , Peter Zijlstra , Borislav Petkov , Greg KH , Kees Cook , Hugh Dickins , Brian Gerst , Josh Poimboeuf , Denys Vlasenko , Boris Ostrovsky , Juergen Gross , David Laight , Eduardo Valentin , "Liguori, Anthony" , Will Deacon , linux-mm On Tue, 12 Dec 2017, Andy Lutomirski wrote: > On Tue, Dec 12, 2017 at 12:37 PM, Thomas Gleixner wrote: > > On Tue, 12 Dec 2017, Dave Hansen wrote: > > > >> On 12/12/2017 11:21 AM, Thomas Gleixner wrote: > >> > The only critical interaction is the return to user path (user CS/SS) and > >> > we made sure with the LAR touching that these are precached in the CPU > >> > before we go into fragile exit code. > >> > >> How do we make sure that it _stays_ cached? > >> > >> Surely there is weird stuff like WBINVD or SMI's that can come at very > >> inconvenient times and wipe it out of the cache. > > > > This does not look like cache in the sense of memory cache. It seems to be > > CPU internal state and I just stuffed WBINVD and alternatively CLFLUSH'ed > > the entries after the 'touch' via LAR. Still works. > > > > There *must* be some weird bug in this series. I find it very hard to > believe that x86 CPUs have a magic cache that caches any part of a > not-actually-in-a-segment-register descriptor entry. There is no bug in the code. There was just a bug in my brain which made me fail to see the obvious. See the other mail. Thanks, tglx -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org