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From: Thomas Gleixner <tglx@linutronix.de>
To: Borislav Petkov <bp@alien8.de>
Cc: Meelis Roos <mroos@linux.ee>,
	Linux Kernel list <linux-kernel@vger.kernel.org>,
	x86@kernel.org, linux-edac@vger.kernel.org,
	Tom Lendacky <thomas.lendacky@amd.com>
Subject: Re: 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64
Date: Wed, 3 Jan 2018 00:07:53 +0100 (CET)	[thread overview]
Message-ID: <alpine.DEB.2.20.1801030001580.1957@nanos> (raw)
In-Reply-To: <20180102212706.5gtevvg4rr7rfy5o@pd.tnic>

On Tue, 2 Jan 2018, Borislav Petkov wrote:
> On Tue, Jan 02, 2018 at 10:49:16PM +0200, Meelis Roos wrote:
> > This is on a socket 939 Athlon64 3500+, with PTI enabled.
> 
> LOL.
> 
> > [  316.384669] mce: [Hardware Error]: Machine check events logged
> > [  316.384698] [Hardware Error]: Corrected error, no action required.
> > [  316.384719] [Hardware Error]: CPU:0 (f:2f:2) MC1_STATUS[-|CE|-|-|AddrV]: 0x9400000000010011
> > [  316.384742] [Hardware Error]: Error Addr: 0x0000ffff81e000e0
> 
> That's the [47:12] slice of the virtual address which it tried to execute.
> 
> According to our map in mm.txt:
> 
> ffff800000000000 - ffff87ffffffffff (=43 bits) guard hole, reserved for hypervisor
> 
> vs
> 
> ffff81e000e0...
> 
> which makes me think: WTF now?!
> 
> I don't see any hypervisor happening in dmesg...

Meelis, can you please enable CONFIG_X86_PTDUMP. If you select M then
please load the resulting module 'debug_pagetables'.

Then please do the following from a shell:

# cat /sys/kernel/debug/page_tables/* >t.txt

and provide the output.

Thanks,

	tglx

  reply	other threads:[~2018-01-02 23:08 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-02 20:49 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64 Meelis Roos
2018-01-02 21:27 ` Borislav Petkov
2018-01-02 23:07   ` Thomas Gleixner [this message]
2018-01-03  9:16     ` Meelis Roos
2018-01-03 12:42       ` Borislav Petkov
2018-01-03 13:17         ` Thomas Gleixner
2018-01-03 13:17           ` Thomas Gleixner
2018-01-03 14:01           ` Meelis Roos
2018-01-03 14:01             ` mroos
2018-01-03 16:22           ` [tip:x86/pti] x86/pti: Make sure the user/kernel PTEs match tip-bot for Thomas Gleixner
2018-02-09 23:30             ` Dave Hansen
2018-02-13 15:59               ` Thomas Gleixner
2018-01-03  7:07   ` 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64 Meelis Roos

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