From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753447AbeACPVf (ORCPT + 1 other); Wed, 3 Jan 2018 10:21:35 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:39757 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752786AbeACPVf (ORCPT ); Wed, 3 Jan 2018 10:21:35 -0500 Date: Wed, 3 Jan 2018 16:21:32 +0100 (CET) From: Thomas Gleixner To: Lars Wendler cc: LKML , x86@kernel.org, Borislav Betkov , Andy Lutomirski , Dave Hansen , Peter Zijlstra , Greg KH Subject: Re: CONFIG_PAGE_TABLE_ISOLATION=y on x86_64 causes gcc to segfault when building x86_32 binaries In-Reply-To: <20180103143036.60e592eb@abudhabi.paradoxon.rec> Message-ID: References: <20180103123723.1dd26828@abudhabi.paradoxon.rec> <20180103143036.60e592eb@abudhabi.paradoxon.rec> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Wed, 3 Jan 2018, Lars Wendler wrote: > Am Wed, 3 Jan 2018 13:05:38 +0100 (CET) > schrieb Thomas Gleixner : > > Also can you please try Linus v4.15-rc6 with PTI enabled so we can see > > whether that's a backport issue or a general one? > > Same problem with 4.15-rc6. So I suppose that means it's a general > issue. Just a shot in the dark as I just decoded another issue on a AMD CPU. Can you please try the patch below? Thanks, tglx 8<--------------- commit 52994c256df36fda9a715697431cba9daecb6b11 Author: Thomas Gleixner Date: Wed Jan 3 15:57:59 2018 +0100 x86/pti: Make sure the user/kernel PTEs match Meelis reported that his K8 Athlon64 emits MCE warnings when PTI is enabled: [Hardware Error]: Error Addr: 0x0000ffff81e000e0 [Hardware Error]: MC1 Error: L1 TLB multimatch. [Hardware Error]: cache level: L1, tx: INSN The address is in the entry area, which is mapped into kernel _AND_ user space. That's special because we switch CR3 while we are executing there. User mapping: 0xffffffff81e00000-0xffffffff82000000 2M ro PSE GLB x pmd Kernel mapping: 0xffffffff81000000-0xffffffff82000000 16M ro PSE x pmd So the K8 is complaining that the TLB entries differ. They differ in the GLB bit. Drop the GLB bit when installing the user shared mapping. Fixes: 6dc72c3cbca0 ("x86/mm/pti: Share entry text PMD") Reported-by: Meelis Roos Signed-off-by: Thomas Gleixner Tested-by: Meelis Roos Cc: Borislav Petkov Cc: Tom Lendacky Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801031407180.1957@nanos diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c index bce8aea65606..2da28ba97508 100644 --- a/arch/x86/mm/pti.c +++ b/arch/x86/mm/pti.c @@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(void) static void __init pti_clone_entry_text(void) { pti_clone_pmds((unsigned long) __entry_text_start, - (unsigned long) __irqentry_text_end, _PAGE_RW); + (unsigned long) __irqentry_text_end, + _PAGE_RW | _PAGE_GLOBAL); } /*