From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754951AbeAMMvJ (ORCPT + 1 other); Sat, 13 Jan 2018 07:51:09 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:36532 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754833AbeAMMvI (ORCPT ); Sat, 13 Jan 2018 07:51:08 -0500 Date: Sat, 13 Jan 2018 13:50:55 +0100 (CET) From: Thomas Gleixner To: Peter Zijlstra cc: Andy Lutomirski , Borislav Petkov , Laura Abbott , X86 ML , Linux Kernel Mailing List , stable Subject: Re: Yet another KPTI regression with 4.14.x series in a VM In-Reply-To: <20180113120847.GI3397@worktop> Message-ID: References: <9eb15489-da09-7a4c-0700-7b6eb99e6f7b@redhat.com> <20180113120847.GI3397@worktop> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Sat, 13 Jan 2018, Peter Zijlstra wrote: > On Fri, Jan 12, 2018 at 10:08:20PM -0800, Andy Lutomirski wrote: > > Now this is quite a strange value to write to CR3. The 0x800 part > > means that we're using the "user" variant of the address space that > > would have ASID=0 and the 0x1000 bit being set corresponds to the user > > pgdir, but this is nonsense, since the kernel never uses PCID 0 for > > user mode. We always start at 1. The only exception is if > > X86_FEATURE_PCID is off. But, if X86_FEATURE_PCID is off, then we > > shouldn't be setting any PCID bits. > > My bad, I was under the impression the lower 12 bits would be ignored > without PCID :/ 2:0 Ignored 3 PWT 4 PCD 11:5 Ignored So yes, it's mostly ignored at least in theory... I'm sure I stared at that code and the SDM more than once and convinced myself that it's not an issue to set bit 11 unconditionally. But I should have stared at the AMD manual which says: Reserved Bits. Reserved fields should be cleared to 0 by software when writing CR3. Thanks, tglx