From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x2243aJ3WJQ0AZV1H05cYWtofY86KhUqDKSEdgcf4S5gheMDz3zm4g2anSOkYNwhM8CsnfU72 ARC-Seal: i=1; a=rsa-sha256; t=1516916273; cv=none; d=google.com; s=arc-20160816; b=FeUy82SvNo1fP6OtCB6Q7Oqph37vAErS0VmIW0Mnbr2ID9J5LHV8jucKKE3fGvK6rq t3qTIOTgVIRlmap/oZjccjPTSragSFT/g8jd9tf6y8XuQU6vs/3xoE74nmBedkbt9YjO l7OOXOgXxU+9FG8tU/vgho7iqdUAwg92et5Ohb2p/Ul2oryqI7egf0UcHtMHqtawdHDa SwY/OCWMcgNIVHilkcMw5SnQdUpt6eVL8hptDCj4bcB4upDQBiFPsG8ZWVtRHRUQsM2o mEQXc5QXb2mhXQRGvSfUerfF85s8MjkyhEmEoB45jxv70j2swJKF77eRqp/o+3qLX4kG wq2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:references:message-id:in-reply-to:subject :cc:to:from:date:arc-authentication-results; bh=KXec/4qQtGFGGTPTM3kdXea4dXcjee+yZRlbHkW4sTQ=; b=EJf3bC4EEm/h2aTE/DYYZSh/5vXU28/tOIyqlotrTY/QmjDIET4a3a73p6YqeyveZB q0/IH8vzWrvKHnpwp5piOJ4GMSFtzDT4S26jFjJoeYHWK6J8YYoyL0f/cC1QSh6LnKJw tbzDdRyZmveEgnaGTpAji3hIqnDY9o0yhg6sc10/dt0Ic2XWOybcC5jSNZWmuvnpsC/V mgHMiBCn+skvrghsv0RAC7ZaCmtiwlKIEuQZ2KRGCsEV3QD/CPIzjgkOCK73ZP1ww3Q+ i5OcgxTJMp0ThdQgJYuatHgAB4yZLAT6C7wPq77STx/UKJSQzDC2emwpXBJ5SaYt9+kp td7g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of tglx@linutronix.de designates 2a01:7a0:2:106d:700::1 as permitted sender) smtp.mailfrom=tglx@linutronix.de Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of tglx@linutronix.de designates 2a01:7a0:2:106d:700::1 as permitted sender) smtp.mailfrom=tglx@linutronix.de Date: Thu, 25 Jan 2018 22:37:30 +0100 (CET) From: Thomas Gleixner To: Borislav Petkov cc: David Woodhouse , Tom Lendacky , arjan@linux.intel.com, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: Re: [PATCH v5 3/7] x86/cpufeatures: Add AMD feature bits for Speculation Control In-Reply-To: <20180125213048.yd5cloxh2ttggeas@pd.tnic> Message-ID: References: <1516896855-7642-1-git-send-email-dwmw@amazon.co.uk> <1516896855-7642-4-git-send-email-dwmw@amazon.co.uk> <20180125213048.yd5cloxh2ttggeas@pd.tnic> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555819438908618?= X-GMAIL-MSGID: =?utf-8?q?1590601997750018442?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Thu, 25 Jan 2018, Borislav Petkov wrote: > + Tom. > > On Thu, Jan 25, 2018 at 04:14:11PM +0000, David Woodhouse wrote: > > AMD exposes the PRED_CMD/SPEC_CTRL MSRs slightly differently to Intel. > > See http://lkml.kernel.org/r/2b3e25cc-286d-8bd0-aeaf-9ac4aae39de8@amd.com > > > > Signed-off-by: David Woodhouse > > Reviewed-by: Greg Kroah-Hartman > > --- > > arch/x86/include/asm/cpufeatures.h | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > > index 0a51070..ae3212f 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -269,6 +269,9 @@ > > #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ > > #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ > > #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ > > +#define X86_FEATURE_AMD_PRED_CMD (13*32+12) /* Prediction Command MSR (AMD) */ > > +#define X86_FEATURE_AMD_SPEC_CTRL (13*32+14) /* Speculation Control MSR only (AMD) */ > > +#define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors (AMD) */ > > So this leaf is AMD-specific so you can drop the AMD strings above. > Also, let's simplify this as those flags appear in /proc/cpuinfo: > > #define X86_FEATURE_IBPB (13*32+12) /* Indirect Branch Prediction Barrier: Prediction Command MSR */ > #define X86_FEATURE_IBRS (13*32+14) /* Speculation Control MSR only */ > #define X86_FEATURE_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */ > > so that we have "ibpb", "ibrs" and "stibp" respectively. That wont work as the intel bits are at a different leave and we cant define the same thing twice.... Thanks, tglx