From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from hsi-kbw-5-158-153-52.hsi19.kabel-badenwuerttemberg.de ([5.158.153.52] helo=nanos.tec.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fIvS9-000373-LW for speck@linutronix.de; Wed, 16 May 2018 14:22:45 +0200 Date: Wed, 16 May 2018 14:22:45 +0200 (CEST) From: Thomas Gleixner Subject: Re: [patch 08/15] Hidden 8 In-Reply-To: <20180516033111.GI18660@char.us.oracle.com> Message-ID: References: <20180513140048.543641807@linutronix.de> <20180513140538.883795088@linutronix.de> <20180516033111.GI18660@char.us.oracle.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Tue, 15 May 2018, speck for Konrad Rzeszutek Wilk wrote: > On Sun, May 13, 2018 at 04:00:56PM +0200, speck for Thomas Gleixner wrote: > > /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ > > #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ > > --- a/arch/x86/include/asm/msr-index.h > > +++ b/arch/x86/include/asm/msr-index.h > > @@ -347,6 +347,8 @@ > > #define MSR_AMD64_SEV_ENABLED_BIT 0 > > #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) > > > > +#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f > > /me scratches his head. this looks off, but it is probably my editor. What looks off? > > } > > #endif > > > > +static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) > > s/amd_// ? I really think this is AMD specific to deal with the fact that the SSBD bit in LS_CFG MSR is on different bit positions depending on the CPU family. which is a pain for guest migration accross host systems with different CPU families. Intel does not have that and they shall burn Inhell if they start to implement that. Let's not try to generalize stuff which should not exist in the first place. Thanks, tglx