From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 13 Jul 2018 09:09:32 -0000 Received: from hsi-kbw-5-158-153-52.hsi19.kabel-badenwuerttemberg.de ([5.158.153.52] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fdu4x-0006x9-6g for speck@linutronix.de; Fri, 13 Jul 2018 11:09:31 +0200 Date: Fri, 13 Jul 2018 11:09:27 +0200 (CEST) From: Thomas Gleixner Subject: Re: [patch V10 10/10] Control knobs and Documentation 10 In-Reply-To: <20180712161330.liz4cdyulklhpvxc@treble> Message-ID: References: <20180712141902.576562442@linutronix.de> <20180712142957.791282859@linutronix.de> <20180712161330.liz4cdyulklhpvxc@treble> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Thu, 12 Jul 2018, speck for Josh Poimboeuf wrote: > On Thu, Jul 12, 2018 at 04:19:12PM +0200, speck for Thomas Gleixner wrote: > > + - L1D Flush mode: > > + > > + ================================ =================================== > > + 'L1D vulnerable' L1D flushing is disabled > > + > > + 'L1D conditional cache flushes' L1D flush is conditionally enabled > > + > > + 'L1D cache flushes' SMT is disabled and L1D flush > > Typo in the description: > > s/SMT is disabled and L1D flush/L1D flushing is unconditionally enabled/ Yeah. Copy and paste is a wonderful tool if used with brain enabled. > > The difference is between 'flush' and 'full' is quite vague here (and in > kernel-parameters.txt). It might be a good idea to give a little more > detail. Done. > It also might be helpful to add a pointer to this document in > kernel-parameters.txt, if the user needs more detail. Done. > > + > > +The default is 'cond'. If 'l1tf=full,force' is given on the kernel command > > +line, then 'always' is enforced and the kvm-intel.vmentry_l1d_flush > > +module parameter is ignored and writes to the sysfs file are rejected. > > I didn't see the disadvantage of 'always' (performance) described > anywhere -- here or in the "L1D flush on VMENTER section". Though maybe > that's obvious... Added a paragraph to the L1D flush section and a link to that section here. Thanks, tglx