From: Thomas Gleixner <tglx@linutronix.de>
To: "Liang, Kan" <kan.liang@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
mingo@redhat.com, acme@kernel.org,
LKML <linux-kernel@vger.kernel.org>,
eranian@google.com, ak@linux.intel.com,
alexander.shishkin@linux.intel.com, x86@kernel.org
Subject: Re: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont
Date: Wed, 3 Oct 2018 15:55:29 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.21.1810031550550.23677@nanos.tec.linutronix.de> (raw)
In-Reply-To: <b3834054-cb2c-2074-7b7d-ad9eb4961a07@linux.intel.com>
On Wed, 3 Oct 2018, Liang, Kan wrote:
> On 10/3/2018 2:10 AM, Thomas Gleixner wrote:
> > There is another variant of model/stepping micro code verification code in
> > intel_snb_pebs_broken(). Can we please make this table based and use a
> > common function? That's certainly not the last quirk we're going to have.
> >
> > We already have a table based variant of ucode checking in
> > bad_spectre_microcode(). It's trivial enough to generalize that.
> >
>
> Sure, I will generalize the bad_spectre_microcode(), rename it to
> is_bad_intel_microcode(), and move it to
> arch\x86\kernel\cpu\microcode\intel.c.
I suggest: is_bad_microcode() and have it in cpu/microcode/core.c unless
you are claiming that bad microcode() is an intel only feature.
> The spectre code and perf code will share the generalized function.
Right. The tables stay in the calling code of course.
Thanks,
tglx
next prev parent reply other threads:[~2018-10-03 13:55 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-02 21:30 [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont kan.liang
2018-10-03 6:10 ` Thomas Gleixner
2018-10-03 13:32 ` Liang, Kan
2018-10-03 13:55 ` Thomas Gleixner [this message]
2018-10-03 14:15 ` Liang, Kan
2018-10-03 14:24 ` Thomas Gleixner
2018-10-03 14:25 ` Liang, Kan
2018-10-03 14:27 ` Borislav Petkov
2018-10-03 14:33 ` Andi Kleen
2018-10-03 15:41 ` Peter Zijlstra
2018-10-03 15:49 ` Borislav Petkov
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