From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08319C43381 for ; Wed, 27 Mar 2019 19:20:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CDF9321734 for ; Wed, 27 Mar 2019 19:20:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387891AbfC0TUE (ORCPT ); Wed, 27 Mar 2019 15:20:04 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:51586 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388208AbfC0TUD (ORCPT ); Wed, 27 Mar 2019 15:20:03 -0400 Received: from p5492e2fc.dip0.t-ipconnect.de ([84.146.226.252] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1h9E5e-0007cz-0l; Wed, 27 Mar 2019 20:19:58 +0100 Date: Wed, 27 Mar 2019 20:19:57 +0100 (CET) From: Thomas Gleixner To: "Ghannam, Yazen" cc: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bp@suse.de" , "tony.luck@intel.com" , "x86@kernel.org" , "rafal@milecki.pl" , "clemej@gmail.com" Subject: Re: [PATCH v4 2/2] x86/MCE/AMD: Don't report L1 BTB MCA errors on some Family 17h models In-Reply-To: <20190325163410.171021-2-Yazen.Ghannam@amd.com> Message-ID: References: <20190325163410.171021-1-Yazen.Ghannam@amd.com> <20190325163410.171021-2-Yazen.Ghannam@amd.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 25 Mar 2019, Ghannam, Yazen wrote: > From: Yazen Ghannam > > AMD Family 17h Models 10h-2Fh may report a high number of L1 BTB MCA > errors under certain conditions. The errors are benign and can safely be > ignored. However, the high error rate may cause the MCA threshold > counter to overflow causing a high rate of thresholding interrupts. In > addition, users may see the errors reported through the AMD MCE decoder > module, even with the interrupt disabled, due to MCA polling. > > This error is reported through the Instruction Fetch bank. > > Clear the "Counter Present" bit in the Instruction Fetch bank's > MCA_MISC0 register. This will prevent enabling MCA thresholding on this > bank which will prevent the high interrupt rate due to this error. > > Define an AMD-specific function to filter these errors from the MCE > event pool. > > Rename filter function in EDAC/mce_amd to avoid a naming conflict. > > Cc: # 5.0.x: c95b323dcd35: x86/MCE/AMD: Turn off MC4_MISC thresholding on all family 0x15 models What is this supposed to tell us? > Cc: # 5.0.x: 30aa3d26edb0: x86/MCE/AMD: Carve out the MC4_MISC thresholding quirk > Cc: # 5.0.x: 9308fd407455: x86/MCE: Group AMD function prototypes in > Cc: # 5.0.x Confused. Thanks, tglx From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v4,2/2] x86/MCE/AMD: Don't report L1 BTB MCA errors on some Family 17h models From: Thomas Gleixner Message-Id: Date: Wed, 27 Mar 2019 20:19:57 +0100 (CET) To: "Ghannam, Yazen" Cc: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bp@suse.de" , "tony.luck@intel.com" , "x86@kernel.org" , "rafal@milecki.pl" , "clemej@gmail.com" List-ID: T24gTW9uLCAyNSBNYXIgMjAxOSwgR2hhbm5hbSwgWWF6ZW4gd3JvdGU6Cgo+IEZyb206IFlhemVu IEdoYW5uYW0gPHlhemVuLmdoYW5uYW1AYW1kLmNvbT4KPiAKPiBBTUQgRmFtaWx5IDE3aCBNb2Rl bHMgMTBoLTJGaCBtYXkgcmVwb3J0IGEgaGlnaCBudW1iZXIgb2YgTDEgQlRCIE1DQQo+IGVycm9y cyB1bmRlciBjZXJ0YWluIGNvbmRpdGlvbnMuIFRoZSBlcnJvcnMgYXJlIGJlbmlnbiBhbmQgY2Fu IHNhZmVseSBiZQo+IGlnbm9yZWQuIEhvd2V2ZXIsIHRoZSBoaWdoIGVycm9yIHJhdGUgbWF5IGNh dXNlIHRoZSBNQ0EgdGhyZXNob2xkCj4gY291bnRlciB0byBvdmVyZmxvdyBjYXVzaW5nIGEgaGln aCByYXRlIG9mIHRocmVzaG9sZGluZyBpbnRlcnJ1cHRzLiBJbgo+IGFkZGl0aW9uLCB1c2VycyBt YXkgc2VlIHRoZSBlcnJvcnMgcmVwb3J0ZWQgdGhyb3VnaCB0aGUgQU1EIE1DRSBkZWNvZGVyCj4g bW9kdWxlLCBldmVuIHdpdGggdGhlIGludGVycnVwdCBkaXNhYmxlZCwgZHVlIHRvIE1DQSBwb2xs aW5nLgo+IAo+IFRoaXMgZXJyb3IgaXMgcmVwb3J0ZWQgdGhyb3VnaCB0aGUgSW5zdHJ1Y3Rpb24g RmV0Y2ggYmFuay4KPiAKPiBDbGVhciB0aGUgIkNvdW50ZXIgUHJlc2VudCIgYml0IGluIHRoZSBJ bnN0cnVjdGlvbiBGZXRjaCBiYW5rJ3MKPiBNQ0FfTUlTQzAgcmVnaXN0ZXIuIFRoaXMgd2lsbCBw cmV2ZW50IGVuYWJsaW5nIE1DQSB0aHJlc2hvbGRpbmcgb24gdGhpcwo+IGJhbmsgd2hpY2ggd2ls bCBwcmV2ZW50IHRoZSBoaWdoIGludGVycnVwdCByYXRlIGR1ZSB0byB0aGlzIGVycm9yLgo+IAo+ IERlZmluZSBhbiBBTUQtc3BlY2lmaWMgZnVuY3Rpb24gdG8gZmlsdGVyIHRoZXNlIGVycm9ycyBm cm9tIHRoZSBNQ0UKPiBldmVudCBwb29sLgo+IAo+IFJlbmFtZSBmaWx0ZXIgZnVuY3Rpb24gaW4g RURBQy9tY2VfYW1kIHRvIGF2b2lkIGEgbmFtaW5nIGNvbmZsaWN0Lgo+IAo+IENjOiA8c3RhYmxl QHZnZXIua2VybmVsLm9yZz4gIyA1LjAueDogYzk1YjMyM2RjZDM1OiB4ODYvTUNFL0FNRDogVHVy biBvZmYgTUM0X01JU0MgdGhyZXNob2xkaW5nIG9uIGFsbCBmYW1pbHkgMHgxNSBtb2RlbHMKCldo YXQgaXMgdGhpcyBzdXBwb3NlZCB0byB0ZWxsIHVzPwoKPiBDYzogPHN0YWJsZUB2Z2VyLmtlcm5l bC5vcmc+ICMgNS4wLng6IDMwYWEzZDI2ZWRiMDogeDg2L01DRS9BTUQ6IENhcnZlIG91dCB0aGUg TUM0X01JU0MgdGhyZXNob2xkaW5nIHF1aXJrCj4gQ2M6IDxzdGFibGVAdmdlci5rZXJuZWwub3Jn PiAjIDUuMC54OiA5MzA4ZmQ0MDc0NTU6IHg4Ni9NQ0U6IEdyb3VwIEFNRCBmdW5jdGlvbiBwcm90 b3R5cGVzIGluIDxhc20vbWNlLmg+Cj4gQ2M6IDxzdGFibGVAdmdlci5rZXJuZWwub3JnPiAjIDUu MC54CgpDb25mdXNlZC4KClRoYW5rcywKCgl0Z2x4Cg==