From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4A2AC5B57D for ; Tue, 2 Jul 2019 06:40:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AA4A420881 for ; Tue, 2 Jul 2019 06:40:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726011AbfGBGkp (ORCPT ); Tue, 2 Jul 2019 02:40:45 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:43540 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725775AbfGBGkp (ORCPT ); Tue, 2 Jul 2019 02:40:45 -0400 Received: from pd9ef1cb8.dip0.t-ipconnect.de ([217.239.28.184] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1hiCSv-0007m3-QT; Tue, 02 Jul 2019 08:40:33 +0200 Date: Tue, 2 Jul 2019 08:40:32 +0200 (CEST) From: Thomas Gleixner To: Wanpeng Li cc: Rong Chen , Feng Tang , the arch/x86 maintainers , LKML , "H. Peter Anvin" , "tipbuild@zytor.com" , "lkp@01.org" , Ingo Molnar , kvm , Paolo Bonzini , =?ISO-8859-2?Q?Radim_Kr=E8m=E1=F8?= , Fenghua Yu Subject: Re: [BUG] kvm: APIC emulation problem - was Re: [LKP] [x86/hotplug] ... In-Reply-To: Message-ID: References: <20190628063231.GA7766@shbuild999.sh.intel.com> <20190630130347.GB93752@shbuild999.sh.intel.com> <20190701083654.GB12486@shbuild999.sh.intel.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Wanpeng, On Tue, 2 Jul 2019, Wanpeng Li wrote: > On Tue, 2 Jul 2019 at 06:44, Thomas Gleixner wrote: > > > > While that CPU0 hotplug test case is surely an esoteric issue, the APIC > > emulation is still wrong, Even if the play_dead() code would not enable > > interrupts then the pending IRR bit would turn into an ISR .. interrupt > > when the APIC is reenabled on startup. > > >From SDM 10.4.7.2 Local APIC State After It Has Been Software Disabled > * Pending interrupts in the IRR and ISR registers are held and require > masking or handling by the CPU. Correct. > In your testing, hardware cpu will not respect soft disable APIC when > IRR has already been set or APICv posted-interrupt is in flight, so we > can skip soft disable APIC checking when clearing IRR and set ISR, > continue to respect soft disable APIC when attempting to set IRR. > Could you try below fix? > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 05d8934..f857a12 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -2376,7 +2376,7 @@ int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) > struct kvm_lapic *apic = vcpu->arch.apic; > u32 ppr; > > - if (!apic_enabled(apic)) > + if (!kvm_apic_hw_enabled(apic)) > return -1; > > __apic_update_ppr(apic, &ppr); Yes. That fixes it and works as expected. Thanks for the quick resolution. I surely stared at that function, but was not sure how to fix it proper. Tested-by: Thomas Gleixner Please add a Cc: stable... tag when you post the patch. Thanks, tglx From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: multipart/mixed; boundary="===============3508413116810149672==" MIME-Version: 1.0 From: Thomas Gleixner To: lkp@lists.01.org Subject: Re: [BUG] kvm: APIC emulation problem - was Re: [x86/hotplug] ... Date: Tue, 02 Jul 2019 08:40:32 +0200 Message-ID: In-Reply-To: List-Id: --===============3508413116810149672== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Wanpeng, On Tue, 2 Jul 2019, Wanpeng Li wrote: > On Tue, 2 Jul 2019 at 06:44, Thomas Gleixner wrote: > > > > While that CPU0 hotplug test case is surely an esoteric issue, the APIC > > emulation is still wrong, Even if the play_dead() code would not enable > > interrupts then the pending IRR bit would turn into an ISR .. interrupt > > when the APIC is reenabled on startup. > = > >From SDM 10.4.7.2 Local APIC State After It Has Been Software Disabled > * Pending interrupts in the IRR and ISR registers are held and require > masking or handling by the CPU. Correct. = > In your testing, hardware cpu will not respect soft disable APIC when > IRR has already been set or APICv posted-interrupt is in flight, so we > can skip soft disable APIC checking when clearing IRR and set ISR, > continue to respect soft disable APIC when attempting to set IRR. > Could you try below fix? > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 05d8934..f857a12 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -2376,7 +2376,7 @@ int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) > struct kvm_lapic *apic =3D vcpu->arch.apic; > u32 ppr; > = > - if (!apic_enabled(apic)) > + if (!kvm_apic_hw_enabled(apic)) > return -1; > = > __apic_update_ppr(apic, &ppr); Yes. That fixes it and works as expected. Thanks for the quick resolution. I surely stared at that function, but was not sure how to fix it proper. Tested-by: Thomas Gleixner Please add a Cc: stable... tag when you post the patch. Thanks, tglx --===============3508413116810149672==--