From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: "Pali Rohár" <pali@kernel.org>
Cc: Stefan Roese <sr@denx.de>, Bin Meng <bmeng.cn@gmail.com>,
Simon Glass <sjg@chromium.org>,
u-boot@lists.denx.de
Subject: Re: [PATCH v2] pci: Do not enable PCIe GEN3 link retrain workaround by default
Date: Sat, 17 Sep 2022 14:03:14 +0100 (BST) [thread overview]
Message-ID: <alpine.DEB.2.21.2209171310150.53071@angie.orcam.me.uk> (raw)
In-Reply-To: <20220830115625.3thq3is5oisqht4p@pali>
On Tue, 30 Aug 2022, Pali Rohár wrote:
> > Agreed. But I also understand the reasoning from Maciej, at least in
> > parts. Thinking a bit more about this, my preference would be to still
> > include this workaround per default in U-Boot proper though. To not
> > make things too complicated here.
> >
> > Just my 0.02$.
>
> I understand it.
>
> Anyway, I would really to know where is the issue (in which part of PCIe
> hierarchy) and what exactly is affected.
Here's the hierarchy tree of the system affected:
-[0000:00]---00.0-[01-0b]----00.0-[02-0b]--+-00.0-[03]--
+-02.0-[04]----00.0
+-03.0-[05-09]----00.0-[06-09]--+-01.0-[07]--+-00.0
| | \-00.3
| \-02.0-[08-09]----00.0-[09]--+-01.0
| \-02.0
+-04.0-[0a]----00.0
\-08.0-[0b]--+-00.0
\-00.1
and the issue is between 0000:02:03.0 and 0000:05:00.0. This has nothing
to do with the host CPU and the ASM2824 part is a generic PCIe switch also
available on option cards with slots. So it can be plugged by a user into
any system out there that has PCIe slot connectivity (also a conventional
PCI system via a PCI-to-PCIe reverse bridge or IIUC a Thunderbolt bridge).
Of course if a given system has no external PCI/e connectivity and no
affected devices onboard, then there is no point in having the workaround
included in the firmware.
> I think that deep understanding of the issue is important or at least
> confirmation from the vendor (which we know that it would not come).
Indeed that would help a lot, but we need to live with what we have.
FWIW I have finally found time and an availability slot with my HiFive
Unmatched hardware to get an updated version of the Linux fix made,
verified and posted upstream; cf.
<https://lore.kernel.org/linux-pci/alpine.DEB.2.21.2209061238050.2275@angie.orcam.me.uk/>.
Maciej
next prev parent reply other threads:[~2022-09-17 13:03 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-06 15:09 [PATCH] pci: Do not enable PCIe ASMedia ASM2824 workaround by default Pali Rohár
2022-04-07 6:33 ` Stefan Roese
2022-04-07 23:18 ` Maciej W. Rozycki
2022-05-01 15:18 ` Pali Rohár
2022-05-05 11:46 ` Maciej W. Rozycki
2022-05-14 13:20 ` Maciej W. Rozycki
2022-08-27 12:30 ` [PATCH v2] pci: Do not enable PCIe GEN3 link retrain " Pali Rohár
2022-08-30 2:30 ` Simon Glass
2022-08-30 9:04 ` Maciej W. Rozycki
2022-08-30 9:19 ` Pali Rohár
2022-08-30 11:15 ` Stefan Roese
2022-08-30 11:56 ` Pali Rohár
2022-09-17 13:03 ` Maciej W. Rozycki [this message]
2022-09-17 13:02 ` Maciej W. Rozycki
2022-09-17 13:02 ` Maciej W. Rozycki
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=alpine.DEB.2.21.2209171310150.53071@angie.orcam.me.uk \
--to=macro@orcam.me.uk \
--cc=bmeng.cn@gmail.com \
--cc=pali@kernel.org \
--cc=sjg@chromium.org \
--cc=sr@denx.de \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.