From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 482E4C5DF61 for ; Thu, 7 Nov 2019 22:32:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0F5F92077C for ; Thu, 7 Nov 2019 22:32:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="QtH1+NFX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726292AbfKGWcE (ORCPT ); Thu, 7 Nov 2019 17:32:04 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:37588 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725946AbfKGWcE (ORCPT ); Thu, 7 Nov 2019 17:32:04 -0500 Received: by mail-pf1-f195.google.com with SMTP id p24so3439481pfn.4 for ; Thu, 07 Nov 2019 14:32:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:from:to:cc:subject:in-reply-to:message-id:references :user-agent:mime-version; bh=ZDZxE3X2u0Q7iWpkFaFMXlQVwx+tT1FJavF2B89FPtQ=; b=QtH1+NFXJ0zzfuKxuEMoDpcPK9ve7QSvHogyfZ1LD7WbXf1vDvHk1gduDooLeS3gSa OQ3Iuy0iZC41baX078kKCIeaia9GMa3KjZi9B/3VjKahrxuaPICa6MWCXjekHjmiy0Y1 SY2EiKmne3GXAJRmsBQsy2QSW4VDhhxYelSb5nKn8Oq0uZBjnmvBdve2KYmQ3tg6cpX9 iDI5aqWNyVmHm4b5vPv1Fe+BH9/fNlR+2jpvh52/fjAPY4wfFFLhpwl5wwhwcMvyUiEg CT/ddVBror3UdtXZOJDJMDyl93GUbm3Cn/qDOnh6C7iuStCKkoIv03sv3cKV9P+MavEw Rc/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:in-reply-to:message-id :references:user-agent:mime-version; bh=ZDZxE3X2u0Q7iWpkFaFMXlQVwx+tT1FJavF2B89FPtQ=; b=aXXMAKefIkGQKpwKSpztXP2G090u6b/DJFScgjLhVnIZE/KUz4Hj8WZFoPqu3kBAHs FruFrouoLHXhoJzZ4ugCAnQ0coGeIdsSK2mt5ikjaY7sA2sjYolb87XHWbzrM3dDRe8O BiNP/PrIYuUNIi+gR4OGU4LojCwqHe5zJ9uN3bnxMQNA3Linyg6mvNyhGnExuy3Sad2M 0ozYrRjfoWojQeHVL9T0vlB2wADJ6wJs2sh27Fe1jhvB8aLs2cbx/LMNh2J7rkMla+W8 Ej9uPAJ1UkOJNLsyivzcySFHVqecOzOpun8ZBzgVpFSDkx5uue/qp199pu7QyOB1MuhX xtyA== X-Gm-Message-State: APjAAAV1SooYw6XH37B3N2FhHwgq1So55SxTxJhcl1uaQrbKUjEIamza LeoGqqDlvmsaJfBEd50QHWHCbA== X-Google-Smtp-Source: APXvYqwls8ddOTQNH1en07qze09B+ck+PA1CQw6LiSffpWOEx3b9mIFdJ4cJ6t90/fOVdQWQ78m/kg== X-Received: by 2002:a63:8f5e:: with SMTP id r30mr7741111pgn.146.1573165923226; Thu, 07 Nov 2019 14:32:03 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id w15sm3662519pfn.13.2019.11.07.14.32.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2019 14:32:02 -0800 (PST) Date: Thu, 7 Nov 2019 14:32:01 -0800 (PST) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: Christoph Hellwig cc: Sebastian Reichel , Rob Herring , Mark Rutland , Palmer Dabbelt , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, peter.maydell@linaro.org Subject: Re: [PATCH 1/2] dt-bindings: power: reset: document the QEMU RISC-V virt machine poweroff device In-Reply-To: <20191107212408.11857-2-hch@lst.de> Message-ID: References: <20191107212408.11857-1-hch@lst.de> <20191107212408.11857-2-hch@lst.de> User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, 7 Nov 2019, Christoph Hellwig wrote: > Add the binding for the trivial Qemu RISC-V poweroff mechanism, which is There's nothing RISC-V specific here. This IP isn't defined in the RISC-V specifications, or anything like that. Apparently it's a SiFive IP block which now has a virtual IP implementation in QEMU in hw/riscv/sifive_test.c. But since there's nothing RISC-V specific about this IP block, any QEMU system, with any CPU implementation, should be able to use this virtual IP, and this Linux driver. For these reasons, it's better if "RISC-V" is just removed from everywhere in this driver. If something needs to go in its place, "SiFive" may be better. - Paul > just a single MMIO register exposed through the DT. > > Signed-off-by: Christoph Hellwig > --- > .../power/reset/qemu-riscv-virt-poweroff.txt | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > create mode 100644 Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt > > diff --git a/Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt b/Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt > new file mode 100644 > index 000000000000..80ff6fd4e3b7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt > @@ -0,0 +1,16 @@ > +QEMU RISC-V virt machine poweroff device > + > +This is a device in Qemu that can signal successful or error exit > +by writing two magic numbers to a trivial mmio register. > +A Linux poweroff is implemented as successful exit. > + > +Required Properties: > +-compatible: "sifive,test0" > +-reg: Specifies the physical address of the register > + > +Example: > + > + test@100000 { > + compatible = "sifive,test0"; > + reg = <0x100000 0x1000>; > + }; > -- > 2.20.1 > > - Paul From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D7F4C5DF60 for ; Thu, 7 Nov 2019 22:32:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4CCA0214D8 for ; Thu, 7 Nov 2019 22:32:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="LuwVZwLH"; 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Thu, 07 Nov 2019 14:32:02 -0800 (PST) Date: Thu, 7 Nov 2019 14:32:01 -0800 (PST) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: Christoph Hellwig Subject: Re: [PATCH 1/2] dt-bindings: power: reset: document the QEMU RISC-V virt machine poweroff device In-Reply-To: <20191107212408.11857-2-hch@lst.de> Message-ID: References: <20191107212408.11857-1-hch@lst.de> <20191107212408.11857-2-hch@lst.de> User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191107_143206_394218_8A436D49 X-CRM114-Status: GOOD ( 17.46 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, peter.maydell@linaro.org, Sebastian Reichel , Rob Herring , Palmer Dabbelt , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, 7 Nov 2019, Christoph Hellwig wrote: > Add the binding for the trivial Qemu RISC-V poweroff mechanism, which is There's nothing RISC-V specific here. This IP isn't defined in the RISC-V specifications, or anything like that. Apparently it's a SiFive IP block which now has a virtual IP implementation in QEMU in hw/riscv/sifive_test.c. But since there's nothing RISC-V specific about this IP block, any QEMU system, with any CPU implementation, should be able to use this virtual IP, and this Linux driver. For these reasons, it's better if "RISC-V" is just removed from everywhere in this driver. If something needs to go in its place, "SiFive" may be better. - Paul > just a single MMIO register exposed through the DT. > > Signed-off-by: Christoph Hellwig > --- > .../power/reset/qemu-riscv-virt-poweroff.txt | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > create mode 100644 Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt > > diff --git a/Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt b/Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt > new file mode 100644 > index 000000000000..80ff6fd4e3b7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt > @@ -0,0 +1,16 @@ > +QEMU RISC-V virt machine poweroff device > + > +This is a device in Qemu that can signal successful or error exit > +by writing two magic numbers to a trivial mmio register. > +A Linux poweroff is implemented as successful exit. > + > +Required Properties: > +-compatible: "sifive,test0" > +-reg: Specifies the physical address of the register > + > +Example: > + > + test@100000 { > + compatible = "sifive,test0"; > + reg = <0x100000 0x1000>; > + }; > -- > 2.20.1 > > - Paul _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv