[PATCH v2 0/4] Spectre BHB follow up

[PATCH v2 0/4] Spectre BHB follow up

[Bertrand Marquis]

Following up the handling of Spectre BHB on Arm (XSA-398), this serie
contain several changes which were not needed in the XSA patches but
should be done in Xen:
- Sync sysregs and cpuinfo with latest version of Linux (5.18-rc3)
- Add new fields inside cpufeature
- Add sb instruction support. Some newer generations of CPU
  (Neoverse-N2) do support the instruction so add support for it in Xen.
- Create hidden Kconfig entries for CONFIG_ values actually used in
  arm64 cpufeature.

Changes in v2
- remove patch which was merged (workaround 1 when workaround 3 is done)
- split sync with linux and update of cpufeatures
- add patch to define kconfig entries used by arm64 cpufeature

Bertrand Marquis (4):
  xen/arm: Sync sysregs and cpuinfo with Linux 5.18-rc3
  xen/arm: Add sb instruction support
  arm: add ISAR2, MMFR0 and MMFR1 fields in cpufeature
  arm: Define kconfig symbols used by arm64 cpufeatures

 xen/arch/arm/Kconfig                     | 28 +++++++++
 xen/arch/arm/arm64/cpufeature.c          | 18 +++++-
 xen/arch/arm/cpufeature.c                | 28 +++++++++
 xen/arch/arm/include/asm/arm64/sysregs.h | 76 ++++++++++++++++++++----
 xen/arch/arm/include/asm/cpufeature.h    | 34 +++++++++--
 xen/arch/arm/include/asm/macros.h        | 33 +++++++---
 xen/arch/arm/setup.c                     |  3 +
 xen/arch/arm/smpboot.c                   |  1 +
 8 files changed, 193 insertions(+), 28 deletions(-)

-- 
2.25.1

[PATCH v2 1/4] xen/arm: Sync sysregs and cpuinfo with Linux 5.18-rc3

[Bertrand Marquis]

Sync existing ID registers sanitization with the status of Linux kernel
version 5.18-rc3 and add sanitization of ISAR2 registers.

Sync sysregs.h bit shift defintions with the status of Linux kernel
version 5.18-rc3.

Changes in this patch are splitted in a number of patches in Linux
kernel and, as the previous synchronisation point was not clear, the
changes are done in one patch with a status possible to compare easily
by diffing Xen files to Linux kernel files.

Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git b2d229d4ddb1
Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
Changes in v2
- move changes in cpufeature.h in an independent patch
- add proper origin tag in the commit
- rework the commit message
---
 xen/arch/arm/arm64/cpufeature.c          | 18 +++++-
 xen/arch/arm/include/asm/arm64/sysregs.h | 76 ++++++++++++++++++++----
 2 files changed, 80 insertions(+), 14 deletions(-)

diff --git a/xen/arch/arm/arm64/cpufeature.c b/xen/arch/arm/arm64/cpufeature.c
index 6e5d30dc7b..d9039d37b2 100644
--- a/xen/arch/arm/arm64/cpufeature.c
+++ b/xen/arch/arm/arm64/cpufeature.c
@@ -143,6 +143,16 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 	ARM64_FTR_END,
 };
 
+static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
+		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
+		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
+	ARM64_FTR_END,
+};
+
 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
@@ -158,8 +168,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
 	ARM64_FTR_END,
 };
 
@@ -197,7 +207,7 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
 	/*
@@ -243,6 +253,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
+	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
@@ -588,6 +599,7 @@ void update_system_features(const struct cpuinfo_arm *new)
 
 	SANITIZE_ID_REG(isa64, 0, aa64isar0);
 	SANITIZE_ID_REG(isa64, 1, aa64isar1);
+	SANITIZE_ID_REG(isa64, 2, aa64isar2);
 
 	SANITIZE_ID_REG(zfr64, 0, aa64zfr0);
 
diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h
index eac08ed33f..54670084c3 100644
--- a/xen/arch/arm/include/asm/arm64/sysregs.h
+++ b/xen/arch/arm/include/asm/arm64/sysregs.h
@@ -144,6 +144,30 @@
 
 /* id_aa64isar2 */
 #define ID_AA64ISAR2_CLEARBHB_SHIFT 28
+#define ID_AA64ISAR2_APA3_SHIFT     12
+#define ID_AA64ISAR2_GPA3_SHIFT     8
+#define ID_AA64ISAR2_RPRES_SHIFT    4
+#define ID_AA64ISAR2_WFXT_SHIFT     0
+
+#define ID_AA64ISAR2_RPRES_8BIT     0x0
+#define ID_AA64ISAR2_RPRES_12BIT    0x1
+/*
+ * Value 0x1 has been removed from the architecture, and is
+ * reserved, but has not yet been removed from the ARM ARM
+ * as of ARM DDI 0487G.b.
+ */
+#define ID_AA64ISAR2_WFXT_NI        0x0
+#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2
+
+#define ID_AA64ISAR2_APA3_NI                  0x0
+#define ID_AA64ISAR2_APA3_ARCHITECTED         0x1
+#define ID_AA64ISAR2_APA3_ARCH_EPAC           0x2
+#define ID_AA64ISAR2_APA3_ARCH_EPAC2          0x3
+#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC     0x4
+#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC_CMB 0x5
+
+#define ID_AA64ISAR2_GPA3_NI             0x0
+#define ID_AA64ISAR2_GPA3_ARCHITECTED    0x1
 
 /* id_aa64pfr0 */
 #define ID_AA64PFR0_CSV3_SHIFT       60
@@ -165,14 +189,13 @@
 #define ID_AA64PFR0_AMU              0x1
 #define ID_AA64PFR0_SVE              0x1
 #define ID_AA64PFR0_RAS_V1           0x1
+#define ID_AA64PFR0_RAS_V1P1         0x2
 #define ID_AA64PFR0_FP_NI            0xf
 #define ID_AA64PFR0_FP_SUPPORTED     0x0
 #define ID_AA64PFR0_ASIMD_NI         0xf
 #define ID_AA64PFR0_ASIMD_SUPPORTED  0x0
-#define ID_AA64PFR0_EL1_64BIT_ONLY   0x1
-#define ID_AA64PFR0_EL1_32BIT_64BIT  0x2
-#define ID_AA64PFR0_EL0_64BIT_ONLY   0x1
-#define ID_AA64PFR0_EL0_32BIT_64BIT  0x2
+#define ID_AA64PFR0_ELx_64BIT_ONLY   0x1
+#define ID_AA64PFR0_ELx_32BIT_64BIT  0x2
 
 /* id_aa64pfr1 */
 #define ID_AA64PFR1_MPAMFRAC_SHIFT   16
@@ -189,6 +212,7 @@
 #define ID_AA64PFR1_MTE_NI           0x0
 #define ID_AA64PFR1_MTE_EL0          0x1
 #define ID_AA64PFR1_MTE              0x2
+#define ID_AA64PFR1_MTE_ASYMM        0x3
 
 /* id_aa64zfr0 */
 #define ID_AA64ZFR0_F64MM_SHIFT      56
@@ -228,17 +252,37 @@
 #define ID_AA64MMFR0_ASID_SHIFT      4
 #define ID_AA64MMFR0_PARANGE_SHIFT   0
 
-#define ID_AA64MMFR0_TGRAN4_NI         0xf
-#define ID_AA64MMFR0_TGRAN4_SUPPORTED  0x0
-#define ID_AA64MMFR0_TGRAN64_NI        0xf
-#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
-#define ID_AA64MMFR0_TGRAN16_NI        0x0
-#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
+#define ID_AA64MMFR0_ASID_8          0x0
+#define ID_AA64MMFR0_ASID_16         0x2
+
+#define ID_AA64MMFR0_TGRAN4_NI             0xf
+#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN  0x0
+#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX  0x7
+#define ID_AA64MMFR0_TGRAN64_NI            0xf
+#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 0x0
+#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 0x7
+#define ID_AA64MMFR0_TGRAN16_NI            0x0
+#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 0x1
+#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 0xf
+
+#define ID_AA64MMFR0_PARANGE_32        0x0
+#define ID_AA64MMFR0_PARANGE_36        0x1
+#define ID_AA64MMFR0_PARANGE_40        0x2
+#define ID_AA64MMFR0_PARANGE_42        0x3
+#define ID_AA64MMFR0_PARANGE_44        0x4
 #define ID_AA64MMFR0_PARANGE_48        0x5
 #define ID_AA64MMFR0_PARANGE_52        0x6
 
+#define ARM64_MIN_PARANGE_BITS     32
+
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE    0x1
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN     0x2
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX     0x7
+
 /* id_aa64mmfr1 */
 #define ID_AA64MMFR1_ECBHB_SHIFT     60
+#define ID_AA64MMFR1_AFP_SHIFT       44
 #define ID_AA64MMFR1_ETS_SHIFT       36
 #define ID_AA64MMFR1_TWED_SHIFT      32
 #define ID_AA64MMFR1_XNX_SHIFT       28
@@ -271,6 +315,9 @@
 #define ID_AA64MMFR2_CNP_SHIFT       0
 
 /* id_aa64dfr0 */
+#define ID_AA64DFR0_MTPMU_SHIFT      48
+#define ID_AA64DFR0_TRBE_SHIFT       44
+#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
 #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
 #define ID_AA64DFR0_PMSVER_SHIFT     32
 #define ID_AA64DFR0_CTX_CMPS_SHIFT   28
@@ -284,11 +331,18 @@
 #define ID_AA64DFR0_PMUVER_8_1       0x4
 #define ID_AA64DFR0_PMUVER_8_4       0x5
 #define ID_AA64DFR0_PMUVER_8_5       0x6
+#define ID_AA64DFR0_PMUVER_8_7       0x7
 #define ID_AA64DFR0_PMUVER_IMP_DEF   0xf
 
+#define ID_AA64DFR0_PMSVER_8_2      0x1
+#define ID_AA64DFR0_PMSVER_8_3      0x2
+
 #define ID_DFR0_PERFMON_SHIFT        24
 
-#define ID_DFR0_PERFMON_8_1          0x4
+#define ID_DFR0_PERFMON_8_0         0x3
+#define ID_DFR0_PERFMON_8_1         0x4
+#define ID_DFR0_PERFMON_8_4         0x5
+#define ID_DFR0_PERFMON_8_5         0x6
 
 #define ID_ISAR4_SWP_FRAC_SHIFT        28
 #define ID_ISAR4_PSR_M_SHIFT           24
-- 
2.25.1

[PATCH v2 2/4] xen/arm: Add sb instruction support

[Bertrand Marquis]

This patch is adding sb instruction support when it is supported by a
CPU on arm64.
A new cpu feature capability system is introduced to enable alternative
code using sb instruction when it is supported by the processor. This is
decided based on the isa64 system register value and use a new hardware
capabitility ARM64_HAS_SB.

The sb instruction is encoded using its hexadecimal value to avoid
recursive macro and support old compilers not having support for sb
instruction.

Arm32 instruction support is added but it is not enabled at the moment
due to the lack of hardware supporting it.

Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
Changes in v2:
- fix commit message
- add comment to explain the extra nop
- add support for arm32 and move macro back to arm generic header
- fix macro comment indentation
- introduce cpu feature system instead of using errata
---
 xen/arch/arm/cpufeature.c             | 28 +++++++++++++++++++++++
 xen/arch/arm/include/asm/cpufeature.h |  6 ++++-
 xen/arch/arm/include/asm/macros.h     | 33 ++++++++++++++++++++-------
 xen/arch/arm/setup.c                  |  3 +++
 xen/arch/arm/smpboot.c                |  1 +
 5 files changed, 62 insertions(+), 9 deletions(-)

diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c
index a58965f7b9..5d1421dc67 100644
--- a/xen/arch/arm/cpufeature.c
+++ b/xen/arch/arm/cpufeature.c
@@ -26,6 +26,24 @@ DECLARE_BITMAP(cpu_hwcaps, ARM_NCAPS);
 
 struct cpuinfo_arm __read_mostly guest_cpuinfo;
 
+#ifdef CONFIG_ARM_64
+static bool has_sb_instruction(const struct arm_cpu_capabilities *entry)
+{
+    return system_cpuinfo.isa64.sb;
+}
+#endif
+
+static const struct arm_cpu_capabilities arm_features[] = {
+#ifdef CONFIG_ARM_64
+    {
+        .desc = "Speculation barrier instruction (SB)",
+        .capability = ARM64_HAS_SB,
+        .matches = has_sb_instruction,
+    },
+#endif
+    {},
+};
+
 void update_cpu_capabilities(const struct arm_cpu_capabilities *caps,
                              const char *info)
 {
@@ -70,6 +88,16 @@ void __init enable_cpu_capabilities(const struct arm_cpu_capabilities *caps)
     }
 }
 
+void check_local_cpu_features(void)
+{
+    update_cpu_capabilities(arm_features, "enabled support for");
+}
+
+void __init enable_cpu_features(void)
+{
+    enable_cpu_capabilities(arm_features);
+}
+
 /*
  * Run through the enabled capabilities and enable() them on the calling CPU.
  * If enabling of any capability fails the error is returned. After enabling a
diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h
index f7368766c0..9649a7afee 100644
--- a/xen/arch/arm/include/asm/cpufeature.h
+++ b/xen/arch/arm/include/asm/cpufeature.h
@@ -67,8 +67,9 @@
 #define ARM_WORKAROUND_BHB_LOOP_24 13
 #define ARM_WORKAROUND_BHB_LOOP_32 14
 #define ARM_WORKAROUND_BHB_SMCC_3 15
+#define ARM64_HAS_SB 16
 
-#define ARM_NCAPS           16
+#define ARM_NCAPS           17
 
 #ifndef __ASSEMBLY__
 
@@ -78,6 +79,9 @@
 
 extern DECLARE_BITMAP(cpu_hwcaps, ARM_NCAPS);
 
+void check_local_cpu_features(void);
+void enable_cpu_features(void);
+
 static inline bool cpus_have_cap(unsigned int num)
 {
     if ( num >= ARM_NCAPS )
diff --git a/xen/arch/arm/include/asm/macros.h b/xen/arch/arm/include/asm/macros.h
index 1aa373760f..33e863d982 100644
--- a/xen/arch/arm/include/asm/macros.h
+++ b/xen/arch/arm/include/asm/macros.h
@@ -5,14 +5,7 @@
 # error "This file should only be included in assembly file"
 #endif
 
-    /*
-     * Speculative barrier
-     * XXX: Add support for the 'sb' instruction
-     */
-    .macro sb
-    dsb nsh
-    isb
-    .endm
+#include <asm/alternative.h>
 
 #if defined (CONFIG_ARM_32)
 # include <asm/arm32/macros.h>
@@ -29,4 +22,28 @@
     .endr
     .endm
 
+    /*
+     * Speculative barrier
+     */
+    .macro sb
+alternative_if_not ARM64_HAS_SB
+    dsb nsh
+    isb
+alternative_else
+    /*
+     * SB encoding in hexadecimal to prevent recursive macro.
+     * extra nop is required to keep same number of instructions on both sides
+     * of the alternative.
+     */
+#if defined(CONFIG_ARM_32)
+    .inst 0xf57ff070
+#elif defined(CONFIG_ARM_64)
+    .inst 0xd50330ff
+#else
+#   error "missing sb encoding for ARM variant"
+#endif
+    nop
+alternative_endif
+    .endm
+
 #endif /* __ASM_ARM_MACROS_H */
diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
index ea1f5ee3d3..b44494c9a9 100644
--- a/xen/arch/arm/setup.c
+++ b/xen/arch/arm/setup.c
@@ -961,6 +961,8 @@ void __init start_xen(unsigned long boot_phys_offset,
      */
     check_local_cpu_errata();
 
+    check_local_cpu_features();
+
     init_xen_time();
 
     gic_init();
@@ -1030,6 +1032,7 @@ void __init start_xen(unsigned long boot_phys_offset,
      */
     apply_alternatives_all();
     enable_errata_workarounds();
+    enable_cpu_features();
 
     /* Create initial domain 0. */
     if ( !is_dom0less_mode() )
diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c
index 9bb32a301a..fb7cc43a93 100644
--- a/xen/arch/arm/smpboot.c
+++ b/xen/arch/arm/smpboot.c
@@ -389,6 +389,7 @@ void start_secondary(void)
     local_abort_enable();
 
     check_local_cpu_errata();
+    check_local_cpu_features();
 
     printk(XENLOG_DEBUG "CPU %u booted.\n", smp_processor_id());
 
-- 
2.25.1

[PATCH v2 3/4] arm: add ISAR2, MMFR0 and MMFR1 fields in cpufeature

[Bertrand Marquis]

Complete AA64ISAR2 and AA64MMFR[0-1] with more fields.
While there add a comment for MMFR bitfields as for other registers in
the cpuinfo structure definition.

Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
Changes in v2:
- patch introduced to isolate changes in cpufeature.h
- complete MMFR0 and ISAR2 to sync with sysregs.h status
---
 xen/arch/arm/include/asm/cpufeature.h | 28 ++++++++++++++++++++++-----
 1 file changed, 23 insertions(+), 5 deletions(-)

diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h
index 9649a7afee..57eb6773d3 100644
--- a/xen/arch/arm/include/asm/cpufeature.h
+++ b/xen/arch/arm/include/asm/cpufeature.h
@@ -234,6 +234,7 @@ struct cpuinfo_arm {
     union {
         register_t bits[3];
         struct {
+            /* MMFR0 */
             unsigned long pa_range:4;
             unsigned long asid_bits:4;
             unsigned long bigend:4;
@@ -242,18 +243,31 @@ struct cpuinfo_arm {
             unsigned long tgranule_16K:4;
             unsigned long tgranule_64K:4;
             unsigned long tgranule_4K:4;
-            unsigned long __res0:32;
-
+            unsigned long tgranule_16k_2:4;
+            unsigned long tgranule_64k_2:4;
+            unsigned long tgranule_4k:4;
+            unsigned long exs:4;
+            unsigned long __res0:8;
+            unsigned long fgt:4;
+            unsigned long ecv:4;
+
+            /* MMFR1 */
             unsigned long hafdbs:4;
             unsigned long vmid_bits:4;
             unsigned long vh:4;
             unsigned long hpds:4;
             unsigned long lo:4;
             unsigned long pan:4;
-            unsigned long __res1:8;
-            unsigned long __res2:28;
+            unsigned long specsei:4;
+            unsigned long xnx:4;
+            unsigned long twed:4;
+            unsigned long ets:4;
+            unsigned long __res1:4;
+            unsigned long afp:4;
+            unsigned long __res2:12;
             unsigned long ecbhb:4;
 
+            /* MMFR2 */
             unsigned long __res3:64;
         };
     } mm64;
@@ -297,7 +311,11 @@ struct cpuinfo_arm {
             unsigned long __res2:8;
 
             /* ISAR2 */
-            unsigned long __res3:28;
+            unsigned long wfxt:4;
+            unsigned long rpres:4;
+            unsigned long gpa3:4;
+            unsigned long apa3:4;
+            unsigned long __res3:12;
             unsigned long clearbhb:4;
 
             unsigned long __res4:32;
-- 
2.25.1

[PATCH v2 4/4] arm: Define kconfig symbols used by arm64 cpufeatures

[Bertrand Marquis]

Define kconfig symbols which are used by arm64 cpufeatures to prevent
using undefined symbols and rely on IS_ENABLED returning false.
All the features related to those symbols are unsupported by Xen:
- pointer authentication
- sve
- memory tagging
- branch target identification

Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
Change in v2:
- patch introduced
---
 xen/arch/arm/Kconfig | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index ecfa6822e4..c9a4e40e9b 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -97,6 +97,34 @@ config HARDEN_BRANCH_PREDICTOR
 
 	  If unsure, say Y.
 
+config ARM64_PTR_AUTH
+	def_bool n
+	depends on ARM64
+	help
+	  Pointer authentication support.
+	  This feature is not supported in Xen.
+
+config ARM64_SVE
+	def_bool n
+	depends on ARM64
+	help
+	  Scalar Vector Extension support.
+	  This feature is not supported in Xen.
+
+config ARM64_MTE
+	def_bool n
+	depends on ARM64
+	help
+	  Memory Tagging Extension support.
+	  This feature is not supported in Xen.
+
+config ARM64_BTI
+	def_bool n
+	depends on ARM64
+	help
+	  Branch Target Identification support.
+	  This feature is not supported in Xen.
+
 config TEE
 	bool "Enable TEE mediators support (UNSUPPORTED)" if UNSUPPORTED
 	default n
-- 
2.25.1

Re: [PATCH v2 3/4] arm: add ISAR2, MMFR0 and MMFR1 fields in cpufeature

[Stefano Stabellini]

On Tue, 31 May 2022, Bertrand Marquis wrote:
> Complete AA64ISAR2 and AA64MMFR[0-1] with more fields.
> While there add a comment for MMFR bitfields as for other registers in
> the cpuinfo structure definition.
> 
> Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
> ---
> Changes in v2:
> - patch introduced to isolate changes in cpufeature.h
> - complete MMFR0 and ISAR2 to sync with sysregs.h status
> ---
>  xen/arch/arm/include/asm/cpufeature.h | 28 ++++++++++++++++++++++-----
>  1 file changed, 23 insertions(+), 5 deletions(-)
> 
> diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h
> index 9649a7afee..57eb6773d3 100644
> --- a/xen/arch/arm/include/asm/cpufeature.h
> +++ b/xen/arch/arm/include/asm/cpufeature.h
> @@ -234,6 +234,7 @@ struct cpuinfo_arm {
>      union {
>          register_t bits[3];
>          struct {
> +            /* MMFR0 */
>              unsigned long pa_range:4;
>              unsigned long asid_bits:4;
>              unsigned long bigend:4;
> @@ -242,18 +243,31 @@ struct cpuinfo_arm {
>              unsigned long tgranule_16K:4;
>              unsigned long tgranule_64K:4;
>              unsigned long tgranule_4K:4;
> -            unsigned long __res0:32;
> -
> +            unsigned long tgranule_16k_2:4;
> +            unsigned long tgranule_64k_2:4;
> +            unsigned long tgranule_4k:4;

Should be tgranule_4k_2:4


> +            unsigned long exs:4;
> +            unsigned long __res0:8;
> +            unsigned long fgt:4;
> +            unsigned long ecv:4;
> +
> +            /* MMFR1 */
>              unsigned long hafdbs:4;
>              unsigned long vmid_bits:4;
>              unsigned long vh:4;
>              unsigned long hpds:4;
>              unsigned long lo:4;
>              unsigned long pan:4;
> -            unsigned long __res1:8;
> -            unsigned long __res2:28;
> +            unsigned long specsei:4;
> +            unsigned long xnx:4;
> +            unsigned long twed:4;
> +            unsigned long ets:4;
> +            unsigned long __res1:4;

hcx?


> +            unsigned long afp:4;
> +            unsigned long __res2:12;

ntlbpa
tidcp1
cmow

>              unsigned long ecbhb:4;

Strangely enough I am looking at DDI0487H and ecbhb is not there
(D13.2.65). Am I looking at the wrong location?


> +            /* MMFR2 */
>              unsigned long __res3:64;
>          };
>      } mm64;
> @@ -297,7 +311,11 @@ struct cpuinfo_arm {
>              unsigned long __res2:8;
>  
>              /* ISAR2 */
> -            unsigned long __res3:28;
> +            unsigned long wfxt:4;
> +            unsigned long rpres:4;
> +            unsigned long gpa3:4;
> +            unsigned long apa3:4;
> +            unsigned long __res3:12;

mops
bc
pac_frac


>              unsigned long clearbhb:4;

And again this is not described at D13.2.63. Probably the bhb stuff
didn't make it into the ARM ARM yet.


>  
>              unsigned long __res4:32;
> -- 
> 2.25.1
> 

Re: [PATCH v2 1/4] xen/arm: Sync sysregs and cpuinfo with Linux 5.18-rc3

[Stefano Stabellini]

On Tue, 31 May 2022, Bertrand Marquis wrote:
> Sync existing ID registers sanitization with the status of Linux kernel
> version 5.18-rc3 and add sanitization of ISAR2 registers.
> 
> Sync sysregs.h bit shift defintions with the status of Linux kernel
> version 5.18-rc3.
> 
> Changes in this patch are splitted in a number of patches in Linux
> kernel and, as the previous synchronisation point was not clear, the
> changes are done in one patch with a status possible to compare easily
> by diffing Xen files to Linux kernel files.
> 
> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git b2d229d4ddb1
> Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>

Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>


> ---
> Changes in v2
> - move changes in cpufeature.h in an independent patch
> - add proper origin tag in the commit
> - rework the commit message
> ---
>  xen/arch/arm/arm64/cpufeature.c          | 18 +++++-
>  xen/arch/arm/include/asm/arm64/sysregs.h | 76 ++++++++++++++++++++----
>  2 files changed, 80 insertions(+), 14 deletions(-)
> 
> diff --git a/xen/arch/arm/arm64/cpufeature.c b/xen/arch/arm/arm64/cpufeature.c
> index 6e5d30dc7b..d9039d37b2 100644
> --- a/xen/arch/arm/arm64/cpufeature.c
> +++ b/xen/arch/arm/arm64/cpufeature.c
> @@ -143,6 +143,16 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
>  	ARM64_FTR_END,
>  };
>  
> +static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
> +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
> +	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
> +		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0),
> +	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
> +		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0),
> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
> +	ARM64_FTR_END,
> +};
> +
>  static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
> @@ -158,8 +168,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
>  	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
> -	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
> -	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
> +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
> +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
>  	ARM64_FTR_END,
>  };
>  
> @@ -197,7 +207,7 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
>  };
>  
>  static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
> -	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
>  	/*
> @@ -243,6 +253,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
>  };
>  
>  static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
> @@ -588,6 +599,7 @@ void update_system_features(const struct cpuinfo_arm *new)
>  
>  	SANITIZE_ID_REG(isa64, 0, aa64isar0);
>  	SANITIZE_ID_REG(isa64, 1, aa64isar1);
> +	SANITIZE_ID_REG(isa64, 2, aa64isar2);
>  
>  	SANITIZE_ID_REG(zfr64, 0, aa64zfr0);
>  
> diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h
> index eac08ed33f..54670084c3 100644
> --- a/xen/arch/arm/include/asm/arm64/sysregs.h
> +++ b/xen/arch/arm/include/asm/arm64/sysregs.h
> @@ -144,6 +144,30 @@
>  
>  /* id_aa64isar2 */
>  #define ID_AA64ISAR2_CLEARBHB_SHIFT 28
> +#define ID_AA64ISAR2_APA3_SHIFT     12
> +#define ID_AA64ISAR2_GPA3_SHIFT     8
> +#define ID_AA64ISAR2_RPRES_SHIFT    4
> +#define ID_AA64ISAR2_WFXT_SHIFT     0
> +
> +#define ID_AA64ISAR2_RPRES_8BIT     0x0
> +#define ID_AA64ISAR2_RPRES_12BIT    0x1
> +/*
> + * Value 0x1 has been removed from the architecture, and is
> + * reserved, but has not yet been removed from the ARM ARM
> + * as of ARM DDI 0487G.b.
> + */
> +#define ID_AA64ISAR2_WFXT_NI        0x0
> +#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2
> +
> +#define ID_AA64ISAR2_APA3_NI                  0x0
> +#define ID_AA64ISAR2_APA3_ARCHITECTED         0x1
> +#define ID_AA64ISAR2_APA3_ARCH_EPAC           0x2
> +#define ID_AA64ISAR2_APA3_ARCH_EPAC2          0x3
> +#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC     0x4
> +#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC_CMB 0x5
> +
> +#define ID_AA64ISAR2_GPA3_NI             0x0
> +#define ID_AA64ISAR2_GPA3_ARCHITECTED    0x1
>  
>  /* id_aa64pfr0 */
>  #define ID_AA64PFR0_CSV3_SHIFT       60
> @@ -165,14 +189,13 @@
>  #define ID_AA64PFR0_AMU              0x1
>  #define ID_AA64PFR0_SVE              0x1
>  #define ID_AA64PFR0_RAS_V1           0x1
> +#define ID_AA64PFR0_RAS_V1P1         0x2
>  #define ID_AA64PFR0_FP_NI            0xf
>  #define ID_AA64PFR0_FP_SUPPORTED     0x0
>  #define ID_AA64PFR0_ASIMD_NI         0xf
>  #define ID_AA64PFR0_ASIMD_SUPPORTED  0x0
> -#define ID_AA64PFR0_EL1_64BIT_ONLY   0x1
> -#define ID_AA64PFR0_EL1_32BIT_64BIT  0x2
> -#define ID_AA64PFR0_EL0_64BIT_ONLY   0x1
> -#define ID_AA64PFR0_EL0_32BIT_64BIT  0x2
> +#define ID_AA64PFR0_ELx_64BIT_ONLY   0x1
> +#define ID_AA64PFR0_ELx_32BIT_64BIT  0x2
>  
>  /* id_aa64pfr1 */
>  #define ID_AA64PFR1_MPAMFRAC_SHIFT   16
> @@ -189,6 +212,7 @@
>  #define ID_AA64PFR1_MTE_NI           0x0
>  #define ID_AA64PFR1_MTE_EL0          0x1
>  #define ID_AA64PFR1_MTE              0x2
> +#define ID_AA64PFR1_MTE_ASYMM        0x3
>  
>  /* id_aa64zfr0 */
>  #define ID_AA64ZFR0_F64MM_SHIFT      56
> @@ -228,17 +252,37 @@
>  #define ID_AA64MMFR0_ASID_SHIFT      4
>  #define ID_AA64MMFR0_PARANGE_SHIFT   0
>  
> -#define ID_AA64MMFR0_TGRAN4_NI         0xf
> -#define ID_AA64MMFR0_TGRAN4_SUPPORTED  0x0
> -#define ID_AA64MMFR0_TGRAN64_NI        0xf
> -#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
> -#define ID_AA64MMFR0_TGRAN16_NI        0x0
> -#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
> +#define ID_AA64MMFR0_ASID_8          0x0
> +#define ID_AA64MMFR0_ASID_16         0x2
> +
> +#define ID_AA64MMFR0_TGRAN4_NI             0xf
> +#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN  0x0
> +#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX  0x7
> +#define ID_AA64MMFR0_TGRAN64_NI            0xf
> +#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 0x0
> +#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 0x7
> +#define ID_AA64MMFR0_TGRAN16_NI            0x0
> +#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 0x1
> +#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 0xf
> +
> +#define ID_AA64MMFR0_PARANGE_32        0x0
> +#define ID_AA64MMFR0_PARANGE_36        0x1
> +#define ID_AA64MMFR0_PARANGE_40        0x2
> +#define ID_AA64MMFR0_PARANGE_42        0x3
> +#define ID_AA64MMFR0_PARANGE_44        0x4
>  #define ID_AA64MMFR0_PARANGE_48        0x5
>  #define ID_AA64MMFR0_PARANGE_52        0x6
>  
> +#define ARM64_MIN_PARANGE_BITS     32
> +
> +#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0
> +#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE    0x1
> +#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN     0x2
> +#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX     0x7
> +
>  /* id_aa64mmfr1 */
>  #define ID_AA64MMFR1_ECBHB_SHIFT     60
> +#define ID_AA64MMFR1_AFP_SHIFT       44
>  #define ID_AA64MMFR1_ETS_SHIFT       36
>  #define ID_AA64MMFR1_TWED_SHIFT      32
>  #define ID_AA64MMFR1_XNX_SHIFT       28
> @@ -271,6 +315,9 @@
>  #define ID_AA64MMFR2_CNP_SHIFT       0
>  
>  /* id_aa64dfr0 */
> +#define ID_AA64DFR0_MTPMU_SHIFT      48
> +#define ID_AA64DFR0_TRBE_SHIFT       44
> +#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
>  #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
>  #define ID_AA64DFR0_PMSVER_SHIFT     32
>  #define ID_AA64DFR0_CTX_CMPS_SHIFT   28
> @@ -284,11 +331,18 @@
>  #define ID_AA64DFR0_PMUVER_8_1       0x4
>  #define ID_AA64DFR0_PMUVER_8_4       0x5
>  #define ID_AA64DFR0_PMUVER_8_5       0x6
> +#define ID_AA64DFR0_PMUVER_8_7       0x7
>  #define ID_AA64DFR0_PMUVER_IMP_DEF   0xf
>  
> +#define ID_AA64DFR0_PMSVER_8_2      0x1
> +#define ID_AA64DFR0_PMSVER_8_3      0x2
> +
>  #define ID_DFR0_PERFMON_SHIFT        24
>  
> -#define ID_DFR0_PERFMON_8_1          0x4
> +#define ID_DFR0_PERFMON_8_0         0x3
> +#define ID_DFR0_PERFMON_8_1         0x4
> +#define ID_DFR0_PERFMON_8_4         0x5
> +#define ID_DFR0_PERFMON_8_5         0x6
>  
>  #define ID_ISAR4_SWP_FRAC_SHIFT        28
>  #define ID_ISAR4_PSR_M_SHIFT           24
> -- 
> 2.25.1
> 

Re: [PATCH v2 0/4] Spectre BHB follow up

[Stefano Stabellini]

I reviewed patches #1 and #3. Julien had already started reviewing the
other patches in details so it is probably better if he continues his
reviews on those. So I skipped them for now. Let me know if you'd like
me to review them.

On Tue, 31 May 2022, Bertrand Marquis wrote:
> Following up the handling of Spectre BHB on Arm (XSA-398), this serie
> contain several changes which were not needed in the XSA patches but
> should be done in Xen:
> - Sync sysregs and cpuinfo with latest version of Linux (5.18-rc3)
> - Add new fields inside cpufeature
> - Add sb instruction support. Some newer generations of CPU
>   (Neoverse-N2) do support the instruction so add support for it in Xen.
> - Create hidden Kconfig entries for CONFIG_ values actually used in
>   arm64 cpufeature.
> 
> Changes in v2
> - remove patch which was merged (workaround 1 when workaround 3 is done)
> - split sync with linux and update of cpufeatures
> - add patch to define kconfig entries used by arm64 cpufeature
> 
> Bertrand Marquis (4):
>   xen/arm: Sync sysregs and cpuinfo with Linux 5.18-rc3
>   xen/arm: Add sb instruction support
>   arm: add ISAR2, MMFR0 and MMFR1 fields in cpufeature
>   arm: Define kconfig symbols used by arm64 cpufeatures
> 
>  xen/arch/arm/Kconfig                     | 28 +++++++++
>  xen/arch/arm/arm64/cpufeature.c          | 18 +++++-
>  xen/arch/arm/cpufeature.c                | 28 +++++++++
>  xen/arch/arm/include/asm/arm64/sysregs.h | 76 ++++++++++++++++++++----
>  xen/arch/arm/include/asm/cpufeature.h    | 34 +++++++++--
>  xen/arch/arm/include/asm/macros.h        | 33 +++++++---
>  xen/arch/arm/setup.c                     |  3 +
>  xen/arch/arm/smpboot.c                   |  1 +
>  8 files changed, 193 insertions(+), 28 deletions(-)
> 
> -- 
> 2.25.1
> 

Re: [PATCH v2 3/4] arm: add ISAR2, MMFR0 and MMFR1 fields in cpufeature

[Bertrand Marquis]

Hi Stefano,

> On 3 Jun 2022, at 02:45, Stefano Stabellini <sstabellini@kernel.org> wrote:
> 
> On Tue, 31 May 2022, Bertrand Marquis wrote:
>> Complete AA64ISAR2 and AA64MMFR[0-1] with more fields.
>> While there add a comment for MMFR bitfields as for other registers in
>> the cpuinfo structure definition.
>> 
>> Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
>> ---
>> Changes in v2:
>> - patch introduced to isolate changes in cpufeature.h
>> - complete MMFR0 and ISAR2 to sync with sysregs.h status
>> ---
>> xen/arch/arm/include/asm/cpufeature.h | 28 ++++++++++++++++++++++-----
>> 1 file changed, 23 insertions(+), 5 deletions(-)
>> 
>> diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h
>> index 9649a7afee..57eb6773d3 100644
>> --- a/xen/arch/arm/include/asm/cpufeature.h
>> +++ b/xen/arch/arm/include/asm/cpufeature.h
>> @@ -234,6 +234,7 @@ struct cpuinfo_arm {
>> union {
>> register_t bits[3];
>> struct {
>> + /* MMFR0 */
>> unsigned long pa_range:4;
>> unsigned long asid_bits:4;
>> unsigned long bigend:4;
>> @@ -242,18 +243,31 @@ struct cpuinfo_arm {
>> unsigned long tgranule_16K:4;
>> unsigned long tgranule_64K:4;
>> unsigned long tgranule_4K:4;
>> - unsigned long __res0:32;
>> -
>> + unsigned long tgranule_16k_2:4;
>> + unsigned long tgranule_64k_2:4;
>> + unsigned long tgranule_4k:4;
> 
> Should be tgranule_4k_2:4

Right I will fix that.

> 
> 
>> + unsigned long exs:4;
>> + unsigned long __res0:8;
>> + unsigned long fgt:4;
>> + unsigned long ecv:4;
>> +
>> + /* MMFR1 */
>> unsigned long hafdbs:4;
>> unsigned long vmid_bits:4;
>> unsigned long vh:4;
>> unsigned long hpds:4;
>> unsigned long lo:4;
>> unsigned long pan:4;
>> - unsigned long __res1:8;
>> - unsigned long __res2:28;
>> + unsigned long specsei:4;
>> + unsigned long xnx:4;
>> + unsigned long twed:4;
>> + unsigned long ets:4;
>> + unsigned long __res1:4;
> 
> hcx?
> 
> 
>> + unsigned long afp:4;
>> + unsigned long __res2:12;
> 
> ntlbpa
> tidcp1
> cmow
> 
>> unsigned long ecbhb:4;
> 
> Strangely enough I am looking at DDI0487H and ecbhb is not there
> (D13.2.65). Am I looking at the wrong location?

Right now I declared here only the values which have a corresponding
declaration in sysregs.h
If I add more fields here we will not be in sync with it anymore.

And on ecbhb it will be in the next revision of the manual yes.


> 
> 
>> + /* MMFR2 */
>> unsigned long __res3:64;
>> };
>> } mm64;
>> @@ -297,7 +311,11 @@ struct cpuinfo_arm {
>> unsigned long __res2:8;
>> 
>> /* ISAR2 */
>> - unsigned long __res3:28;
>> + unsigned long wfxt:4;
>> + unsigned long rpres:4;
>> + unsigned long gpa3:4;
>> + unsigned long apa3:4;
>> + unsigned long __res3:12;
> 
> mops
> bc
> pac_frac
> 
> 
>> unsigned long clearbhb:4;
> 
> And again this is not described at D13.2.63. Probably the bhb stuff
> didn't make it into the ARM ARM yet.

As said before, are you ok with only adding stuff declared in sysregs
to make it simpler to sync with Linux ?

Cheers
Bertrand

> 
> 
>> 
>> unsigned long __res4:32;
>> -- 
>> 2.25.1

Re: [PATCH v2 3/4] arm: add ISAR2, MMFR0 and MMFR1 fields in cpufeature

[Stefano Stabellini]

On Mon, 6 Jun 2022, Bertrand Marquis wrote:
> Hi Stefano,
> 
> > On 3 Jun 2022, at 02:45, Stefano Stabellini <sstabellini@kernel.org> wrote:
> > 
> > On Tue, 31 May 2022, Bertrand Marquis wrote:
> >> Complete AA64ISAR2 and AA64MMFR[0-1] with more fields.
> >> While there add a comment for MMFR bitfields as for other registers in
> >> the cpuinfo structure definition.
> >> 
> >> Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
> >> ---
> >> Changes in v2:
> >> - patch introduced to isolate changes in cpufeature.h
> >> - complete MMFR0 and ISAR2 to sync with sysregs.h status
> >> ---
> >> xen/arch/arm/include/asm/cpufeature.h | 28 ++++++++++++++++++++++-----
> >> 1 file changed, 23 insertions(+), 5 deletions(-)
> >> 
> >> diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h
> >> index 9649a7afee..57eb6773d3 100644
> >> --- a/xen/arch/arm/include/asm/cpufeature.h
> >> +++ b/xen/arch/arm/include/asm/cpufeature.h
> >> @@ -234,6 +234,7 @@ struct cpuinfo_arm {
> >> union {
> >> register_t bits[3];
> >> struct {
> >> + /* MMFR0 */
> >> unsigned long pa_range:4;
> >> unsigned long asid_bits:4;
> >> unsigned long bigend:4;
> >> @@ -242,18 +243,31 @@ struct cpuinfo_arm {
> >> unsigned long tgranule_16K:4;
> >> unsigned long tgranule_64K:4;
> >> unsigned long tgranule_4K:4;
> >> - unsigned long __res0:32;
> >> -
> >> + unsigned long tgranule_16k_2:4;
> >> + unsigned long tgranule_64k_2:4;
> >> + unsigned long tgranule_4k:4;
> > 
> > Should be tgranule_4k_2:4
> 
> Right I will fix that.
> 
> > 
> > 
> >> + unsigned long exs:4;
> >> + unsigned long __res0:8;
> >> + unsigned long fgt:4;
> >> + unsigned long ecv:4;
> >> +
> >> + /* MMFR1 */
> >> unsigned long hafdbs:4;
> >> unsigned long vmid_bits:4;
> >> unsigned long vh:4;
> >> unsigned long hpds:4;
> >> unsigned long lo:4;
> >> unsigned long pan:4;
> >> - unsigned long __res1:8;
> >> - unsigned long __res2:28;
> >> + unsigned long specsei:4;
> >> + unsigned long xnx:4;
> >> + unsigned long twed:4;
> >> + unsigned long ets:4;
> >> + unsigned long __res1:4;
> > 
> > hcx?
> > 
> > 
> >> + unsigned long afp:4;
> >> + unsigned long __res2:12;
> > 
> > ntlbpa
> > tidcp1
> > cmow
> > 
> >> unsigned long ecbhb:4;
> > 
> > Strangely enough I am looking at DDI0487H and ecbhb is not there
> > (D13.2.65). Am I looking at the wrong location?
> 
> Right now I declared here only the values which have a corresponding
> declaration in sysregs.h
> If I add more fields here we will not be in sync with it anymore.
> 
> And on ecbhb it will be in the next revision of the manual yes.
> 
> 
> > 
> > 
> >> + /* MMFR2 */
> >> unsigned long __res3:64;
> >> };
> >> } mm64;
> >> @@ -297,7 +311,11 @@ struct cpuinfo_arm {
> >> unsigned long __res2:8;
> >> 
> >> /* ISAR2 */
> >> - unsigned long __res3:28;
> >> + unsigned long wfxt:4;
> >> + unsigned long rpres:4;
> >> + unsigned long gpa3:4;
> >> + unsigned long apa3:4;
> >> + unsigned long __res3:12;
> > 
> > mops
> > bc
> > pac_frac
> > 
> > 
> >> unsigned long clearbhb:4;
> > 
> > And again this is not described at D13.2.63. Probably the bhb stuff
> > didn't make it into the ARM ARM yet.
> 
> As said before, are you ok with only adding stuff declared in sysregs
> to make it simpler to sync with Linux ?

Yes, that makes sense. In that case just fix tgranule_4k_2 and you can
add my

Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>

Re: [PATCH v2 4/4] arm: Define kconfig symbols used by arm64 cpufeatures

[Julien Grall]

Hi Bertrand,

On 31/05/2022 11:43, Bertrand Marquis wrote:
> Define kconfig symbols which are used by arm64 cpufeatures to prevent
> using undefined symbols and rely on IS_ENABLED returning false.
> All the features related to those symbols are unsupported by Xen:
> - pointer authentication
> - sve
> - memory tagging
> - branch target identification
> 
> Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>

Acked-by: Julien Grall <jgrall@amazon.com>

Cheers,

-- 
Julien Grall

Re: [PATCH v2 2/4] xen/arm: Add sb instruction support

[Julien Grall]

Hi Bertrand,

On 31/05/2022 11:43, Bertrand Marquis wrote:
> diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h
> index f7368766c0..9649a7afee 100644
> --- a/xen/arch/arm/include/asm/cpufeature.h
> +++ b/xen/arch/arm/include/asm/cpufeature.h
> @@ -67,8 +67,9 @@
>   #define ARM_WORKAROUND_BHB_LOOP_24 13
>   #define ARM_WORKAROUND_BHB_LOOP_32 14
>   #define ARM_WORKAROUND_BHB_SMCC_3 15
> +#define ARM64_HAS_SB 16

The feature is for both 32-bit and 64-bit. So I would prefer if it is 
called ARM_HAS_SB.

>   
> -#define ARM_NCAPS           16
> +#define ARM_NCAPS           17
>   
>   #ifndef __ASSEMBLY__
>   
> @@ -78,6 +79,9 @@
>   
>   extern DECLARE_BITMAP(cpu_hwcaps, ARM_NCAPS);
>   
> +void check_local_cpu_features(void);
> +void enable_cpu_features(void);
> +
>   static inline bool cpus_have_cap(unsigned int num)
>   {
>       if ( num >= ARM_NCAPS )
> diff --git a/xen/arch/arm/include/asm/macros.h b/xen/arch/arm/include/asm/macros.h
> index 1aa373760f..33e863d982 100644
> --- a/xen/arch/arm/include/asm/macros.h
> +++ b/xen/arch/arm/include/asm/macros.h
> @@ -5,14 +5,7 @@
>   # error "This file should only be included in assembly file"
>   #endif
>   
> -    /*
> -     * Speculative barrier
> -     * XXX: Add support for the 'sb' instruction
> -     */
> -    .macro sb
> -    dsb nsh
> -    isb
> -    .endm

Looking at the patch bcab2ac84931 "xen/arm64: Place a speculation 
barrier following an ret instruction", the macro was defined before 
including <asm/arm*/macros.h> so 'sb' could be used in macros defined by 
the headers.

I can't remember whether I chose the order because I had a failure on 
some compilers. However, I couldn't find anything in the assembler 
documentation suggesting that a macro A could use B before it is used.

So I would rather avoid to move the macro if there are no strong 
argument for it.

> +#include <asm/alternative.h>
>   
>   #if defined (CONFIG_ARM_32)
>   # include <asm/arm32/macros.h>
> @@ -29,4 +22,28 @@
>       .endr
>       .endm
>   
> +    /*
> +     * Speculative barrier
> +     */
> +    .macro sb
> +alternative_if_not ARM64_HAS_SB
> +    dsb nsh
> +    isb
> +alternative_else
> +    /*
> +     * SB encoding in hexadecimal to prevent recursive macro.
> +     * extra nop is required to keep same number of instructions on both sides
> +     * of the alternative.
> +     */
> +#if defined(CONFIG_ARM_32)
> +    .inst 0xf57ff070
> +#elif defined(CONFIG_ARM_64)
> +    .inst 0xd50330ff
> +#else
> +#   error "missing sb encoding for ARM variant"
> +#endif
> +    nop
> +alternative_endif
> +    .endm
> +
>   #endif /* __ASM_ARM_MACROS_H */
> diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
> index ea1f5ee3d3..b44494c9a9 100644
> --- a/xen/arch/arm/setup.c
> +++ b/xen/arch/arm/setup.c
> @@ -961,6 +961,8 @@ void __init start_xen(unsigned long boot_phys_offset,
>        */
>       check_local_cpu_errata();
>   
> +    check_local_cpu_features();
> +
>       init_xen_time();
>   
>       gic_init();
> @@ -1030,6 +1032,7 @@ void __init start_xen(unsigned long boot_phys_offset,
>        */
>       apply_alternatives_all();
>       enable_errata_workarounds();
> +    enable_cpu_features();
>   
>       /* Create initial domain 0. */
>       if ( !is_dom0less_mode() )
> diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c
> index 9bb32a301a..fb7cc43a93 100644
> --- a/xen/arch/arm/smpboot.c
> +++ b/xen/arch/arm/smpboot.c
> @@ -389,6 +389,7 @@ void start_secondary(void)
>       local_abort_enable();
>   
>       check_local_cpu_errata();
> +    check_local_cpu_features();
>   
>       printk(XENLOG_DEBUG "CPU %u booted.\n", smp_processor_id());
>   

Cheers,

-- 
Julien Grall

Re: [PATCH v2 2/4] xen/arm: Add sb instruction support

[Bertrand Marquis]

Hi Julien,

> On 10 Jun 2022, at 19:20, Julien Grall <julien@xen.org> wrote:
> 
> Hi Bertrand,
> 
> On 31/05/2022 11:43, Bertrand Marquis wrote:
>> diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h
>> index f7368766c0..9649a7afee 100644
>> --- a/xen/arch/arm/include/asm/cpufeature.h
>> +++ b/xen/arch/arm/include/asm/cpufeature.h
>> @@ -67,8 +67,9 @@
>>  #define ARM_WORKAROUND_BHB_LOOP_24 13
>>  #define ARM_WORKAROUND_BHB_LOOP_32 14
>>  #define ARM_WORKAROUND_BHB_SMCC_3 15
>> +#define ARM64_HAS_SB 16
> 
> The feature is for both 32-bit and 64-bit. So I would prefer if it is called ARM_HAS_SB.

Right make sense.

> 
>>  -#define ARM_NCAPS           16
>> +#define ARM_NCAPS           17
>>    #ifndef __ASSEMBLY__
>>  @@ -78,6 +79,9 @@
>>    extern DECLARE_BITMAP(cpu_hwcaps, ARM_NCAPS);
>>  +void check_local_cpu_features(void);
>> +void enable_cpu_features(void);
>> +
>>  static inline bool cpus_have_cap(unsigned int num)
>>  {
>>      if ( num >= ARM_NCAPS )
>> diff --git a/xen/arch/arm/include/asm/macros.h b/xen/arch/arm/include/asm/macros.h
>> index 1aa373760f..33e863d982 100644
>> --- a/xen/arch/arm/include/asm/macros.h
>> +++ b/xen/arch/arm/include/asm/macros.h
>> @@ -5,14 +5,7 @@
>>  # error "This file should only be included in assembly file"
>>  #endif
>>  -    /*
>> -     * Speculative barrier
>> -     * XXX: Add support for the 'sb' instruction
>> -     */
>> -    .macro sb
>> -    dsb nsh
>> -    isb
>> -    .endm
> 
> Looking at the patch bcab2ac84931 "xen/arm64: Place a speculation barrier following an ret instruction", the macro was defined before including <asm/arm*/macros.h> so 'sb' could be used in macros defined by the headers.
> 
> I can't remember whether I chose the order because I had a failure on some compilers. However, I couldn't find anything in the assembler documentation suggesting that a macro A could use B before it is used.
> 
> So I would rather avoid to move the macro if there are no strong argument for it.

Sure I will put it back where it was.

Cheers
Bertrand