From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756344Ab1CBJ1w (ORCPT ); Wed, 2 Mar 2011 04:27:52 -0500 Received: from www.tglx.de ([62.245.132.106]:43369 "EHLO www.tglx.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755989Ab1CBJ1u (ORCPT ); Wed, 2 Mar 2011 04:27:50 -0500 Date: Wed, 2 Mar 2011 10:27:34 +0100 (CET) From: Thomas Gleixner To: "TK, Pratheesh Gangadhar" cc: "linux-kernel@vger.kernel.org" , "hjk@hansjkoch.de" , "gregkh@suse.de" , "sshtylyov@mvista.com" , "arnd@arndb.de" , "Chatterjee, Amit" , "davinci-linux-open-source@linux.davincidsp.com" , "linux-arm-kernel@lists.infradead.org" Subject: RE: [PATCH v7 1/1] PRUSS UIO driver support In-Reply-To: Message-ID: References: <1299014895-2022-1-git-send-email-pratheesh@ti.com> <1299014895-2022-2-git-send-email-pratheesh@ti.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2 Mar 2011, TK, Pratheesh Gangadhar wrote: > > From: Thomas Gleixner [mailto:tglx@linutronix.de] > > > + /* Disable interrupt */ > > > + iowrite32((val & ~intr_mask), intren_reg); > > I checked more on this and actually INTC h/w has Host Interrupt > Enable Indexed Set Register (HIEISR) and Host Interrupt Enable Indexed > Clear Register(HIEICR) which I can use to enable/disable interrupts > without doing RMW. I will use these registers and then we don't need > all the spinlock and irqcontrol stuff. So I need to do > > iowrite32((intr_bit, HIEICR);// This disable the interrupt bit > in intern_reg. > > Userspace can use HIEISR to re-enable the interrupt. Great, that makes it way simpler! > > It's not the purpose of a review to tell you what you need to change > > mechanically. Reviewers hint to a correct solution and you are > > supposed to lookup what that solution means and act accordingly. If > > you do not understand the hint or its implications please ask _before_ > > sending a new patch set. > > Seriously, I went to "fix the comments" mode. Sorry about that. Anyway > I learnt more about things by making mistakes i.e. the positive side. > Thanks a lot for helping us improve on this. Welcome! tglx From mboxrd@z Thu Jan 1 00:00:00 1970 From: tglx@linutronix.de (Thomas Gleixner) Date: Wed, 2 Mar 2011 10:27:34 +0100 (CET) Subject: [PATCH v7 1/1] PRUSS UIO driver support In-Reply-To: References: <1299014895-2022-1-git-send-email-pratheesh@ti.com> <1299014895-2022-2-git-send-email-pratheesh@ti.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, 2 Mar 2011, TK, Pratheesh Gangadhar wrote: > > From: Thomas Gleixner [mailto:tglx at linutronix.de] > > > + /* Disable interrupt */ > > > + iowrite32((val & ~intr_mask), intren_reg); > > I checked more on this and actually INTC h/w has Host Interrupt > Enable Indexed Set Register (HIEISR) and Host Interrupt Enable Indexed > Clear Register(HIEICR) which I can use to enable/disable interrupts > without doing RMW. I will use these registers and then we don't need > all the spinlock and irqcontrol stuff. So I need to do > > iowrite32((intr_bit, HIEICR);// This disable the interrupt bit > in intern_reg. > > Userspace can use HIEISR to re-enable the interrupt. Great, that makes it way simpler! > > It's not the purpose of a review to tell you what you need to change > > mechanically. Reviewers hint to a correct solution and you are > > supposed to lookup what that solution means and act accordingly. If > > you do not understand the hint or its implications please ask _before_ > > sending a new patch set. > > Seriously, I went to "fix the comments" mode. Sorry about that. Anyway > I learnt more about things by making mistakes i.e. the positive side. > Thanks a lot for helping us improve on this. Welcome! tglx