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Date:   Fri, 7 Oct 2016 18:39:42 +0100 (BST)
From:   "Maciej W. Rozycki" <macro@linux-mips.org>
To:     David Daney <ddaney.cavm@gmail.com>
cc:     James Hogan <james.hogan@imgtec.com>,
        Matt Redfearn <matt.redfearn@imgtec.com>,
        Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: [PATCH 1/9] MIPS: traps: 64bit kernels should read CP0_EBase
 64bit
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On Fri, 7 Oct 2016, David Daney wrote:

> > >   Indeed, but we need to be prepared to handle the width of 64 bits and
> > > `cpu_has_mips64r6' does not seem to me to be the right condition.
> >
> > It is not the proper condition.
> >
> > The presence of a 64-bit EBase should be probed for.
> >
> > The proper check is to test of the EBase[WG] (bit 11) can be set to 1.
> > It it can, this indicates that EBase supports 64-bit accesses.

 Indeed; the problem however is it is destructive, because:

1. Until you have probed for it you cannot use 64-bit DMFC0 to record the 
   old value of EBase.

2. By using 32-bit MFC0 to record it you miss the upper 32 bits of EBase.

3. And you do need to use 32-bit MTC0 to set WG with this probing, which 
   clobbers the upper 32 bits of EBase.

So from MIPSr3 through to MIPSr5 you cannot really use the setting left 
there in EBase by the firmware unless it has also left the WG bit set.

> In r5 systems, the only time 64-bit Ebase is really interesting is for
> virtualization.
> 
> You could also gate probing WG on the presence of the VZ capability.

 Still this is an approximation only, the architecture permits 64-bit 
EBase without VZ.

  Maciej